9.1.1 Driving the VIN and V_DD Pins of the ADS7887 and ADS7888

The VIN input to the ADS7887 and ADS7888 must be driven with a low impedance source. In most cases additional buffers are not required. In cases where the source impedance exceeds 200 Ω, using a buffer would help achieve the rated performance of the converter. The THS4031 is a good choice for the driver amplifier buffer.

The reference voltage for the ADS7887 and ADS7888 A/D converters are derived from the supply voltage internally. The devices offer limited low-pass filtering functionality on-chip. The supply to these converters must be driven with a low impedance source and must be decoupled to the ground. A 1-µF storage capacitor and a 10-nF decoupling capacitor must be placed close to the device. Wide, low impedance traces must be used to connect the capacitor to the pins of the device. The ADS7887 and ADS7888 draw very little current from the supply lines. The supply line can be driven by either:

• Directly from the system supply.
• A reference output from a low drift and low dropout reference voltage generator like REF3030 or REF3130. The ADS7887 and ADS7888 can operate off a wide range of supply voltages. The actual choice of the reference voltage generator would depend upon the system. Figure 41 shows one possible application circuit.
• A low-pass filtered version of the system supply followed by a buffer like the zero-drift OPA735 can also be used in cases where the system power supply is noisy. Take care to ensure that the voltage at the V_DD input does not exceed 7 V (especially during power up) to avoid damage to the converter. This can be done easily using single-supply CMOS amplifiers like the OPA735. Figure 42 shows one possible application circuit.

Figure 31. Typical Equivalent Sampling Circuit

9.3.1 ADS7887 Operation

The cycle begins with the falling edge of CS. This point is indicated as a in Figure 32. With the falling edge of CS, the input signal is sampled and the conversion process is initiated. The device outputs data while the conversion is in progress. The data word contains 4 leading zeros, followed by 10-bit data in MSB first format and padded by 2 lagging zeros.

The falling edge of CS clocks out the first zero, and a zero is clocked out on every falling edge of the clock until the third edge. Data is in MSB first format with the MSB being clocked out on the 4th falling edge. Data is padded with two lagging zeros as shown in Figure 32. On the 16th falling edge of SCLK, SDO goes to the 3-state condition. The conversion ends on the 14th falling edge of SCLK. The device enters the acquisition phase on the first rising edge of SCLK after the 13th falling edge. This point is indicated by b in Figure 32.

CS can be asserted (pulled high) after 16 clocks have elapsed. It is necessary not to start the next conversion by pulling CS low until the end of the quiet time (t_q) after SDO goes to 3-state. To continue normal operation, it is necessary that CS is not pulled high until point b. Without this, the device does not enter the acquisition phase and no valid data is available in the next cycle (refer to Power-Down Mode for more details). CS going high any time after the conversion start aborts the ongoing conversion and SDO goes to 3-state.

The high level of the digital input to the device is not limited to device V_DD. This means the digital input can go as high as 5.25 V when the device supply is 2.35 V. This feature is useful when digital signals are coming from another circuit with different supply levels. Also, this relaxes the restriction on power-up sequencing. However, the digital output levels (V_OH and V_OL) are governed by V_DD as listed in Specifications.

Figure 32. ADS7887 Interface Timing Diagram

9.3.2 ADS7888 Operation

The cycle begins with the falling edge of CS . This point is indicated as a in Figure 33. With the falling edge of CS, the input signal is sampled and the conversion process is initiated. The device outputs data while the conversion is in progress. The data word contains 4 leading zeros, followed by 8-bit data in MSB first format and padded by 4 lagging zeros.

The falling edge of CS clocks out the first zero, and a zero is clocked out on every falling edge of the clock until the third edge. Data is in MSB first format with the MSB being clocked out on the 4th falling edge. Data is padded with four lagging zeros as shown in Figure 33. On the 16th falling edge of SCLK, SDO goes to the 3-state condition. The conversion ends on the 12th falling edge of SCLK. The device enters the acquisition phase on the first rising edge of SCLK after the 11th falling edge. This point is indicated by b in Figure 33.

CS can be asserted (pulled high) after 16 clocks have elapsed. It is necessary not to start the next conversion by pulling CS low until the end of the quiet time (t_q) after SDO goes to 3-state. To continue normal operation, it is necessary that CS is not pulled high until point b. Without this, the device does not enter the acquisition phase and no valid data is available in the next cycle (refer to Power-Down Mode for more details). CS going high any time after the conversion start aborts the ongoing conversion and SDO goes to 3-state.

The high level of the digital input to the device is not limited to device V_DD. This means the digital input can go as high as 5.25 V when the device supply is 2.35 V. This feature is useful when digital signals are coming from another circuit with different supply levels. Also, this relaxes the restriction on power-up sequencing. However, the digital output levels (V_OH and V_OL) are governed by V_DD as listed in Specifications.

Figure 33. ADS7888 Interface Timing Diagram

As shown in Figure 34, the ADS7888 can achieve 1.5-MSPS throughput. CS can be pulled high after the 12th falling edge (with a 25-MHz SCLK). SDO goes to 3-state after the LSB (as CS is high). CS can be pulled low at the end of the quiet time (t_q) after SDO goes to 3-state.

Figure 34. ADS7888 Interface Timing Diagram, Data Transfer With 12-Clock Frame

9.4.1 Power-Down Mode

The device enters power-down mode if CS goes high anytime after the 2nd SCLK falling edge to before the 10th SCLK falling edge. Ongoing conversion stops and SDO goes to 3-state under this power-down condition as shown in Figure 35.

Figure 35. Entering Power-Down Mode

A dummy cycle with CS low for more than 10 SCLK falling edges brings the device out of power-down mode. For the device to come to the fully powered-up condition it takes 0.8 µs. CS can be pulled high any time after the 10th falling edge as shown in Figure 36. It is not necessary to continue until the 16th clock if the next conversion starts 0.8 µs after CS going low of the dummy cycle and the quiet time (t_q) condition is met.

Figure 36. Exiting Power-Down Mode