8.5.1 16-Clock Frame

Figure 47 through Figure 49 illustrate the devices operating in 16-clock mode. This mode is the fastest mode for device operation. In this mode, the devices output data from previous conversions while converting the recently sampled signal.

As shown in Figure 47, the ADS7947 starts acquisition of the analog input from the 14th rising edge of SCLK. The device samples the input signal on the CS falling edge. SDO comes out of 3-state and the device outputs the MSB on the CS falling edge. The device outputs the next lower SDO bits on every SCLK falling edge after the SCLK rising edge. The data correspond to the sample and conversion completed in the previous frame. During a CS low period, the device converts the recently sampled signal and uses SCLK for conversions. The number of clocks needed for a conversion for 12-bit and 8-bit devices are different. For the ADS7947, conversion is complete on the 14th SCLK rising edge. CS can be high at any time after the 14th SCLK rising edge. The CS rising edge after the 14th SCLK rising edge and before the 29th SCLK falling edge keeps the device in the 16-clock data frame. The device output goes to 3-state with CS high.

Figure 47. ADS7947 Operating in 16-Clock Mode Without Power-Down (PDEN = 0)

SCLK can also be stopped after the 14th SCLK rising edge.

Figure 48 and Figure 49 illustrate the 16-clock mode operation for the ADS7948 and ADS7949, respectively. The operation for these 10-bit and 8-bit devices is identical to the ADS7947 except that the conversion ends on different edges of SCLK. For the ADS7948, the conversion ends and acquisition starts on the 11th SCLK rising edge. For the ADS7949, the device uses the ninth SCLK rising edge for the conversion end and acquisition start. Similar to the ADS7947, CS can go high and SCLK can be stopped when the device enters acquisition.

Figure 48. ADS7948 Operating in 16-Clock Mode Without Power-Down (PDEN = 0)

Figure 49. ADS7949 Operating in 16-Clock Mode Without Power-Down (PDEN = 0)