JAJSHX7A September   2010  – September 2019 ADS7947 , ADS7948 , ADS7949

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     ADS794x のブロック図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions: ADS794x (12-, 10-, 8-Bit)
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: ADS7947 (12-Bit)
    6. 7.6  Electrical Characteristics: ADS7948 (10-Bit)
    7. 7.7  Electrical Characteristics: ADS7949 (8-Bit)
    8. 7.8  Timing Requirements
    9. 7.9  Switching Characteristics
    10. 7.10 Typical Characteristics: ADS7947, ADS7948, ADS7949
    11. 7.11 Typical Characteristics: ADS7947 (12-Bit)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Multiplexer and ADC Input
      2. 8.3.2 Reference
      3. 8.3.3 Clock
      4. 8.3.4 ADC Transfer Function
      5. 8.3.5 Power-Down
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Operation
    5. 8.5 Programming
      1. 8.5.1 16-Clock Frame
      2. 8.5.2 32-Clock Frame
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Driving an ADC Without a Driving Op Amp
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 関連リンク
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5.2 32-Clock Frame

Figure 50 through Figure 52 illustrate the devices operating in 32-clock mode. In this mode, the devices convert and output the data from the most recent sample before taking the next sample.

ADS7947 ADS7948 ADS7949 ai_tim_32clk_7947_las708.gifFigure 50. ADS7947 Operation in 32-Clock Frame Without Power-Down (PDEN = 0)
ADS7947 ADS7948 ADS7949 ai_tim_32clk_7948_las708.gifFigure 51. ADS7948 Operating in 32-Clock Frame Without Power-Down (PDEN = 0)
ADS7947 ADS7948 ADS7949 ai_tim_32clk_7949_las708.gifFigure 52. ADS7949 Operating in 32-Clock Frame Without Power-Down (PDEN = 0)

CS can be held low past the 16th falling edge of SCLK. The device continues to output recently converted data starting with the 16th SCLK falling edge. If CS is held low until the 30th SCLK falling edge, then the device detects 32-clock mode. The device data from recent conversions are already out with no latency before the 30th SCLK falling edge. When 32-clock mode is detected, the device outputs 16 zeros during the next conversion (in fact, for the first 16 clocks), unlike 16-clock mode where the device outputs the previous conversion result. SCLK can be stopped after the device has seen the 30th falling edge with CS low.