JAJSFU8D November 2017 – June 2024 ADS8166 , ADS8167 , ADS8168
PRODUCTION DATA
This register selects the optimal offset calibration when using an external reference input. When using an internal reference, do not write to this register. See the Reference section for more details.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | REF_SEL[2:0] | ||
R-0b | R-0b | R-0b | R-0b | R-0b | R/W-000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-3 | 0 | R | 0 0000b | Reserved bits. Reads return 0 0000b. |
2-0 | REF_SEL[2:0] | R/W | 000b | These bits select the external reference range for
optimal offset. 000b = Optimum offset calibration for VREF = 5.0V 001b = Optimum offset calibration for VREF = 4.5V 010b = Optimum offset calibration for VREF = 4.096V 011b = Optimum offset calibration for VREF = 3.3V 100b = Optimum offset calibration for VREF = 3.0V 101b = Optimum offset calibration for VREF = 2.5V 110b = Optimum offset calibration for VREF = 5.0V 111b = Optimum offset calibration for VREF = 5.0V |