JAJSFU8D November 2017 – June 2024 ADS8166 , ADS8167 , ADS8168
PRODUCTION DATA
This register selects the SPI protocol for writing data to the device. Write access to this register is disabled on power-up. To enable write access, configure the REG_ACCESS register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | SDI_MODE[1:0] | |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R/W-00b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | R | 000000b | Reserved bits. Do not write. Reads return 000000b. |
1-0 | SDI_MODE[1:0] | R/W | 00b | These bits select the protocol for writing data into the device. 00b = Standard SPI with CPOL = 0 and CPHASE = 0 01b = Standard SPI with CPOL = 0 and CPHASE = 1 10b = Standard SPI with CPOL = 1 and CPHASE = 0 11b = Standard SPI with CPOL = 1 and CPHASE = 1 |