JAJSFU8D November 2017 – June 2024 ADS8166 , ADS8167 , ADS8168
PRODUCTION DATA
This register configures the contents of the output data word. Write access to this register is disabled on power-up. To enable write access, configure the REG_ACCESS register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | DATA_OUT_FORMAT[1:0] | 0 | 0 | 0 | DATA_VAL | |
R-0b | R-0b | R/W-00b | R-0b | R-0b | R-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | 00 | R | 000b | Reserved bits. Reads return 00b. |
5-4 | DATA_OUT_FORMAT[1:0] | R/W | 00b | These bits control the composition of the output data
frame. 00b = ADC conversion result 01b = ADC conversion result + 4-bit channel ID 10b = ADC conversion result + 4-bit channel ID + 4-bit device status (see Table 7-24) + 2-bit channel configuration 11b = Reserved Parity bits are appended to the data output frame. See the PARITY_CNTL register for details. |
3-1 | 000 | R | 000b | Reserved bits. Reads return 00b. |
0 | DATA_VAL | R/W | 0b | Setting this bit enables debug mode for SDO capture. 0b = Normal operation; device data are output on SDO 1b = The device outputs a fixed xA5A5 patten that is useful for debugging data capture from the device |