10.1.1.1 Reference Driver Circuit for V_REF = 4.096 V

The application circuit in Figure 50 shows the schematic of a complete reference driver circuit that generates a voltage of 4.096-V DC using a single 5-V supply. This circuit is suitable to drive the reference of the ADS8332 at the maximum throughput of 500 kSPS. The reference voltage of 4.096 V in this design is generated by the low-power, low drift, low-power REF2041 circuit. The output broadband noise of the reference is filtered by a low-pass filter with a 3-dB cutoff frequency of 159 Hz.

Figure 50. Reference Driver Schematic for VA = 5 V, V_REF = 4.096 V

The OPA320 is a precision, high bandwidth (20 MHz), low-noise (7 nV / √Hz) operational amplifier. The low-noise, and low power consumption of this amplifier makes the OPA320 a good choice to drive the reference input of the ADS833x. The REF+ input is bypassed with a 22-μF bypass capacitor. The 22-µF reference bypass capacitor is high enough to make the OPA320 amplifier unstable, therefore a small resistor (R_{BUF_FLT}) is required to isolate the amplifier output and improve stability. The value of R_{BUF_FLT} is dependent on the output impedance of the driving amplifier as well as the circuit frequency response. Typical values of R_{BUF_FLT} range from 0.1 Ω to 2 Ω and the exact value can be found by using SPICE simulations. In the case of the OPA320 in the reference driver example in Figure 50, the value of R_{BUF_FLT} is 220 mΩ providing >55° of phase margin while driving the 22-µF bypass capacitor. It should be noted that higher values of R_{BUF_FLT} cause high voltage spikes at the reference pin which affects the conversion accuracy.

10.1.1.2 Reference Driver Circuit for V_REF=2.5 V, VA=2.7 V

The circuit shown in Figure 51 can be used to generate a 3-V reference using a 3.3-V supply. This circuit is suitable to drive the reference of the ADS8332 at the maximum throughput of 500 kSPS. The reference voltage of 3 V in this design is generated by the low-power, low drift, REF2025. The output broadband noise of the reference is filtered by a low-pass filter with a 3-dB cutoff frequency of 159 Hz.

Figure 51. Reference Driver Schematic for VA = 2.7 V, V_REF = 2.5 V

10.1.2.1 Input Amplifier Selection

The selection criteria for the input driver amplifier is dependent on the input signal type and the performance goals of the data acquisition system. Some key amplifier specifications to consider while selecting an appropriate amplifier to drive the inputs of the ADC are:

• Small-signal bandwidth: Select the small-signal bandwidth of the input amplifiers to be as high as possible after meeting the power budget of the system. Higher bandwidth reduces the closed-loop output impedance of the amplifier, thus allowing the amplifier to more easily drive the RC filter at the ADC inputs. Higher bandwidth also minimizes the harmonic distortion at higher input frequencies. To maintain the overall stability of the input driver circuit, the amplifier bandwidth should be selected as described in Equation 2:
Equation 2.
• Noise: Noise contribution of the front-end amplifiers should be as low as possible to prevent any degradation in SNR performance of the system. As a rule of thumb, to ensure that the noise performance of the data acquisition system is not limited by the front-end circuit, the total noise contribution from the front-end circuit should be kept below 20% of the input-referred noise of the ADC. Noise from the input driver circuit is band- limited by designing a low cutoff frequency RC filter and is calculated by Equation 3:
Equation 3.
where
• V_{1 / f_AMP_PP} is the peak-to-peak flicker noise in µV
• e_{n_RMS} is the amplifier broadband noise density in nV / √Hz
• f_–3dB is the 3-dB bandwidth of the RC filter
• NG is the noise gain of the front-end circuit, which is equal to 1 in a buffer configuration
• Distortion: Both the ADC and the input driver introduce non-linearity in a data acquisition block. As a rule of thumb, to ensure that the distortion performance of the data acquisition system is not limited by the front-end circuit, the distortion of the input driver should be at least 10-dB lower than the distortion of the ADC, as shown in Equation 4:
Equation 4.
• Settling Time: For DC signals with fast transients that are common in a multiplexed application, the input signal must settle to the desired accuracy at the inputs of the ADC during the acquisition time window. This condition is critical to maintain the overall linearity performance of the ADC. Typically, the amplifier data sheets specify the output settling performance only up to 0.01% with a resistive load which may not be sufficient for the desired accuracy. Therefore, the settling behavior of the input driver with the RC filter load should always be verified by TINA™- SPICE simulations before selecting the amplifier.

10.1.2.2 ADC Input RC Filter

An RC filter is designed as a low-pass, RC filter, for which the 3-dB bandwidth is optimized based on specific application requirements. For DC signals with fast transients (including multiplexed input signals), a high-bandwidth filter is designed to allow accurate settling of the signal at the ADC inputs during the small acquisition time window. For AC signals, the filter bandwidth should be kept low to band-limit the noise fed into the ADC input, thereby increasing the signal-to- noise ratio (SNR) of the system.

A filter capacitor, C_FLT, connected across the ADC inputs (as shown in Figure 52), reduces the noise from the front-end drive circuitry, minimizes the effects of the sampling charge injection and provides a charge bucket to quickly charge the internal sample-and-hold capacitors during the acquisition process. As a rule of thumb, the value of this capacitor should be at least 10 times the specified value of the ADC sampling capacitance. For these devices, the input sampling capacitance is equal to 45 pF. Thus, the value of C_FLT should be greater than 450 pF. For applications measuring AC signals, COG (NPO) ceramic capacitors provide the best capacitance precision. The type of dielectric used in COG (NPO) ceramic capacitors provides the most stable electrical properties over voltage, frequency, and temperature changes.

Driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier marginally unstable. To avoid amplifier stability issues, series isolation resistors (R_FLT) are used at the output of the amplifiers. A higher value of R_FLT is helpful from the amplifier stability perspective, but adds distortion as a result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance, input signal frequency, and input signal amplitude. Therefore, the selection of R_FLT requires balancing the stability and distortion of the design. For low distortion applications, TI recommends limiting the value of R_FLT to a maximum of 50 Ω to avoid any significant degradation in linearity and THD performance.

The input amplifier bandwidth should be much higher than the cutoff frequency of the anti-aliasing filter. TI strongly recommends performing a SPICE simulation to confirm that the amplifier has more than 40° phase margin with the selected RC filter.

Figure 52. ADC Input RC Filter

10.2.1.1 Design Requirements

This section describes an application circuit (Figure 53) optimized for using the ADS833x with lowest noise and distortion performance at ADC throughput of 500kSPS across all channels, using Manual Trigger mode with Auto-Nap mode disabled. The throughput per channel is dependent on the number of channels selected in the multiplexer scanning sequence. For example, the throughput per channel is equal to 250 kSPS if two channels are selected, but it is equal to 125 kSPS per channel if four channels are selected in the sequence and so forth.

10.2.1.2 Detailed Design Procedure

The signal is processed by a low noise, low distortion, operational amplifier in the non-inverting configuration and a low-pass RC filter before being fed into the ADC. The OPA320 features rail-to-rail input operation with a zero-crossover distortion topology that eliminates the transition region typical in many rail-to-rail complementary input stage amplifiers making it ideal to use in the non-inverting configuration. As a rule of thumb, the distortion from the input driver should be at least 10-dB less than the ADC distortion. Therefore, the driver circuit uses the low-power, wide bandwidth (20 MHz) OPA320 as an input driver, which provides exceptional AC performance because of its low-noise, and low distortion specifications. In addition, the components of the RC filter are selected such that the noise from the front-end circuit is limited without adding distortion to the input signal. Driver Amplifier Choice lists some more driver amplifier choices for applications that require high throughput operation with minimum acquisition time.

10.2.1.3 Application Curve

Figure 54 shows the FFT test results obtained with the ADS833x operating at full throughput of 500 kSPS and the circuit configuration of Figure 53.

Figure 54. FFT Plot Showing Performance of ADS8331, ADS8332 With a 10-kHz Input Signal at 500 kSPS

10.2.2.1 Design Requirements

This section describes an application circuit (Figure 55) optimized for using the ADS8332 in low power, low throughput applications for monitoring static or DC signals. A single OPA320 amplifier and passive filter (R₁, C₁) is placed between the MUXOUT and ADCIN inputs driving the ADS8332, while operating the ADC at a reduced data rate.

10.2.2.2 Detailed Design Procedure

The ADS833x offers the flexibility to place an amplifier between the MUXOUT and ADCIN pins. In this case, the operational amplifier between the multiplexer output and ADC input pin must have optimum transient response to charge the internal sampling capacitor (45 pF) and settle within 1 LSB after a full-scale step within the allowed acquisition time.

Placing an amplifier as a buffer between the multiplexer output and the ADC input helps to relax the source impedance requirements at the INx multiplexer inputs. However, it should be noted that there is a parasitic capacitance associated with the MUXOUT pin (approximately 5 pF). This is in addition to the input capacitance of the buffer amplifier placed between MUXOUT and ADCIN pins. This capacitance is switched from one channel to the next during the scan operation and must be recharged to new input channel voltage every time the multiplexer switches channels. Therefore, take care so the previously converted channel charge stored at the MUXOUT capacitance does not disturb the charge of the newly switched channel. This error can be reduced by placing a large enough capacitor at each (INx) multiplexer input.

The data acquisition circuit in Figure 55 is optimized for using the ADS8332 in low power, low throughput applications for monitoring static or DC signals. A single OPA320 amplifier and passive filter (R₁, C₁) is placed between the MUXOUT and ADCIN inputs driving the ADS8332, while operating the ADC at a reduced data rate. The OPA320 offers optimal settling time, DC precision and low noise at a relatively low power consumption (1.5 mA). In this case, the R1C1 is filter is designed to settle within ±1LSB in less than 1 µs after a full-scale input is applied. The ADC is operating at a reduced data rate of less than 250 kSPS in Manual Trigger Mode with Auto-NAP disabled (inactive) to allow a longer acquisition time.

Each multiplexer input is buffered with an ultralow power OPA333 to isolate the source impedance at the multiplexer inputs. A large capacitor Cx is placed at each INx input. The OPA320 has an estimated input capacitance of approximately 9 pF, and the capacitance associated with the MUXOUT pin is approximately 5 pF. The Cx capacitor is many times larger than the parasitic capacitance present at the MUXOUT pin to reduce the effect of charge injection due to the previously converted channel. The OPA333 consumes a maximum quiescent current of 25 µA per amplifier while providing low drift, excellent stability and DC performance at ultra low power consumption. To save power, this circuit is operated on a single 2.7-V supply. The OPA333 circuit is optimal for low-power, low-throughput applications measuring DC signals. When scanning through multiplexer channels ensure to limit the maximum sampling rate per channel to <10kSPS.