JAJSGS3B January   2019  – July 2022 ADS8353-Q1

PRODUCTION DATA  

  1. 1特長
  2. 2アプリケーション
  3. 3概要
  4. 4Revision History
  5. 5Pin Configuration and Functions
  6. 6Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagram
    9. 6.9 Typical Characteristics
  7. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Reference
      2. 7.3.2 Analog Inputs
        1. 7.3.2.1 Analog Input: Full-Scale Range Selection
        2. 7.3.2.2 Analog Input: Single-Ended and Pseudo-Differential Configurations
      3. 7.3.3 Transfer Function
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Write to User-Programmable Registers
      3. 7.5.3 Data Read Operation
        1. 7.5.3.1 Reading User-Programmable Registers
        2. 7.5.3.2 Conversion Data Read
          1. 7.5.3.2.1 32-CLK, Dual-SDO Mode (CFR.B11 = 0, CFR.B10 = 0, Default)
          2. 7.5.3.2.2 32-CLK, Single-SDO Mode (CFR.B11 = 0, CFR.B10 = 1)
      4. 7.5.4 Low-Power Modes
        1. 7.5.4.1 STANDBY Mode
        2. 7.5.4.2 Software Power-Down (SPD) Mode
      5. 7.5.5 Frame Abort, Reconversion, or Short-Cycling
    6. 7.6 Register Maps
      1. 7.6.1 ADS8353-Q1 Registers
  8. 8Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Amplifier Selection
      2. 8.1.2 Charge Kickback Filter
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
      1.      Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.3 Transfer Function

The device supports two input configurations:

  1. Single-ended inputs, CFR.B7 = 0 (default), or
  2. Pseudo-differential inputs, CFR.B7 = 1

 

The device also supports two output data formats:

  1. Straight binary output, CFR.B4 = 0 (default), or
  2. Two's compliment output, CFR.B4 = 1

Equation 5 calculates the device resolution:

 

Equation 5. 1 LSB = (FSR_ADC_x) / (2N)

where:

  • N = 16
  • FSR_ADC_x = the full-scale input range of the ADC (see the Section 7.3.2 section for more details)

 

Table 7-2 and Table 7-3 show the different input voltages and the corresponding output codes from the device.

Table 7-2 Transfer Characteristics for Straight Binary Output (CFR.B4 = 0, Default)
INPUT CONFIGURATIONINPUT VOLTAGEOUTPUT CODE (Hex)
STRAIGHT BINARY (CFR.B4 = 0, Default)
AINP_xAINM_xAINP_x - AINM_xCODEADS8353-Q1
Single-ended
(CFR.B7 = 0, default)		≤ 1 LSB0≤ 1 LSBZC0000
FSR_ADC_x / 2FSR_ADC_x / 2MC7FFF
≥ FSR_ADC_x – 1 LSB≥ FSR_ADC_x – 1 LSBFSCFFFF
Pseudo-differential
(CFR.B7 = 1)		≤ 1 LSBFSR_ADC_x / 2≤ –FSR_ADC_x / 2 + 1 LSBZC0000
FSR_ADC_x / 20MC7FFF
≥ FSR_ADC_x – 1 LSB≥ FSR_ADC_x / 2 – 1 LSBFSCFFFF
Table 7-3 Transfer Characteristics for Two's Compliment Output (CFR.B4 = 1)
INPUT CONFIGURATIONINPUT VOLTAGEOUTPUT CODE (Hex)
TWO'S COMPLIMENT (CFR.B4 = 1, Default)
AINP_xAINM_xAINP_x - AINM_xCODEADS8353-Q1
Single-ended
(CFR.B7 = 0, default)		≤ 1 LSB0≤ 1 LSBNFSC8000
FSR_ADC_x / 2FSR_ADC_x / 2MC0000
≥ FSR_ADC_x – 1 LSB≥ FSR_ADC_x – 1 LSBPFSC7FFF
Pseudo-differential
(CFR.B7 = 1)		≤ 1 LSBFSR_ADC_x / 2≤ –FSR_ADC_x / 2 + 1 LSBNFSC8000
FSR_ADC_x / 20MC0000
≥ FSR_ADC_x – 1 LSB≥ FSR_ADC_x / 2 – 1 LSBPFSC7FFF

Figure 7-3 shows the ideal device transfer characteristics for the single-ended analog input.

GUID-5055C95B-B701-42E1-8790-16419A110501-low.gifFigure 7-3 Ideal Transfer Characteristics for a Single-Ended Analog Input

Figure 7-4 shows the ideal device transfer characteristics for the pseudo-differential analog input.

GUID-B92CF3BE-1D10-469E-94B6-1D22442F8C89-low.gifFigure 7-4 Ideal Transfer Characteristics for a Pseudo-Differential Analog Input