JAJSII2A February   2020  – February 2020 ADS8355

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なブロック図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1      Absolute Maximum Ratings
    2. 6.2      ESD Ratings
    3. 6.3      Recommended Operating Conditions
    4. 6.4      Thermal Information
    5. 6.5      Electrical Characteristics
    6. Table 1. Timing Requirements
    7. Table 2. Switching Characteristics
    8. 6.6      Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Reference
      2. 7.3.2 Analog Inputs
        1. 7.3.2.1 Analog Input: Full-Scale Range Selection
        2. 7.3.2.2 Analog Input: Single-Ended and Pseudo-Differential Configurations
      3. 7.3.3 Transfer Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 Conversion Data Read: Dual-SDO Mode (Default)
      2. 7.4.2 Conversion Data Read: Single-SDO Mode
      3. 7.4.3 Low-Power Modes
        1. 7.4.3.1 STANDBY Mode
        2. 7.4.3.2 PD (Power-Down) Mode
    5. 7.5 Programming
      1. 7.5.1 Register Read/Write Operation
    6. 7.6 Register Map
      1. 7.6.1 ADS8355 Registers
        1. 7.6.1.1  PD_STANDBY Register (Offset = 4h) [reset = 0h]
          1. Table 9. PD_STANDBY Register Field Descriptions
        2. 7.6.1.2  PD_KEY Register (Offset = 5h) [reset = 0h]
          1. Table 10. PD_KEY Register Field Descriptions
        3. 7.6.1.3  SDO_CTRL Register (Offset = Dh) [reset = 0h]
          1. Table 11. SDO_CTRL Register Field Descriptions
        4. 7.6.1.4  DATA_OUT_CTRL Register (Offset = 11h) [reset = 0h]
          1. Table 12. DATA_OUT_CTRL Register Field Descriptions
        5. 7.6.1.5  REF_SEL Register (Offset = 20h) [reset = 0h]
          1. Table 13. REF_SEL Register Field Descriptions
        6. 7.6.1.6  REFDAC_A_LSB Register (Offset = 24h) [reset = 0h]
          1. Table 14. REFDAC_A_LSB Register Field Descriptions
        7. 7.6.1.7  REFDAC_A_MSB Register (Offset = 25h) [reset = 0h]
          1. Table 15. REFDAC_A_MSB Register Field Descriptions
        8. 7.6.1.8  REFDAC_B_LSB Register (Offset = 26h) [reset = 0h]
          1. Table 16. REFDAC_B_LSB Register Field Descriptions
        9. 7.6.1.9  REFDAC_B_MSB Register (Offset = 27h) [reset = 0h]
          1. Table 17. REFDAC_B_MSB Register Field Descriptions
        10. 7.6.1.10 INPUT_CONFIG Register (Offset = 28h) [reset = 0h]
          1. Table 18. INPUT_CONFIG Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Amplifier Selection
      2. 8.1.2 Charge Kickback Filter
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

at AVDD = 5 V, DVDD = 2.35 V to 5.5 V, VREFIO_A = VREFIO_B = 5 V (external) and fSAMPLE = 1 MSPS (unless otherwise noted); minimum and maximum values at TA = –40°C to 125°C; typical values are at TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RESOLUTION
Resolution 16 Bits
DC ACCURACY
NMC No missing codes 16 Bits
INL Integral nonlinearity –3 ±1 3 LSB
VREF input range, internal VREF = 2.5 V ±1
DNL Differential nonlinearity –0.99 ±0.5 0.99 LSB
VREF input range, internal VREF = 2.5 V ±0.5
EIO Input offset error –1 ±0.5 1 mV
EIO match ADC_A to ADC_B –1 ±0.5 1
dEIO/dT Input offset thermal drift 1 µV/°C
EG Gain error Referenced to the voltage at REFIO_x –0.1 ±0.05 0.1 %FS
EG match ADC_A to ADC_B –0.1 ±0.05 0.1
dEG/dT Gain error thermal drift Referenced to the voltage at REFIO_x ±1 ppm/°C
AC ACCURACY
SNR Signal-to-noise ratio VREF input range 86 88 dB
AVDD = 3.3 V, VREF input range, internal VREF = 2.5 V 84
VREF = 2.5 V internal / external, 2 x VREF input range 84
THD Total harmonic distortion VREF input range –97 dB
AVDD = 3.3 V, VREF input range, internal VREF = 2.5 V –97
VREF = 2.5 V internal/external, 2 x VREF input range –97
SINAD Signal-to-noise + distortion VREF input range 87.5 dB
AVDD = 3.3 V, VREF input range, internal VREF = 2.5 V 83
VREF = 2.5 V internal / external, 2 x VREF input range 83
SFDR Spurious-free dynamic range VREF input range 100 dB
AVDD = 3.3 V, VREF input range, internal VREF = 2.5 V 100
VREF = 2.5 V internal/external, 2 x VREF input range 100
ANALOG INPUTS
Ci Input capacitance In sample mode 40 pF
In hold mode 4
Ilkg Input leakage current 0.1 µA
INTERNAL VOLTAGE REFERENCE
VREFIO_x Reference output voltage REFDAC_x = 1FFh at 25°C 2.5 V
VREF-match VREF_A to VREF_B matching REFDAC_x = 1FFh at 25°C ±3 mV
CREFIO Reference output capacitor 10 µF
tREFON Reference output settling time 8 ms
VOLTAGE REFERENCE INPUT
IREF Average reference input current Per ADC 300 µA
CREF External reference capacitor 10 µF
Ilkg(dc) DC leakage current ±0.1 µA
SAMPLING DYNAMICS
tA Aperture delay 8 ns
tA match ADC_A to ADC_B 40 ps
tAJIT Aperture jitter 50 ps
DIGITAL INPUTS
VIH(1) High-level input voltage DVDD ≥ 2.35 V 0.7 x DVDD DVDD + 0.3 V
DVDD < 2.35 V 0.8 x DVDD DVDD + 0.3
VIL(1) Low-level input voltage DVDD ≥ 2.35 V –0.3 0.3 x  DVDD V
DVDD < 2.35 V –0.3 0.2 x DVDD
Input current ±10 nA
DIGITAL OUTPUTS
VOH(1) High-level output voltage IOH = 500-µA source 0.8 x DVDD DVDD V
VOL(1) Low-level output voltage IOL = 500-µA sink 0 0.2 x DVDD V
POWER SUPPLY
AIDD Analog supply current 11 13 mA
AVDD = 5 V, internal reference 12
AVDD = 5V, no conversion internal reference 8
AVDD = 5 V, no conversion external reference(2) 7
AVDD = 5 V, STANDBY mode internal reference 2.5
AVDD = 5 V, STANDBY mode external reference(2) 1
Power-down mode 10 50 µA
DIDD Digital supply current DVDD = 3.3 V, Cload = 10 pF 0.5 mA
DVDD = 5 V, Cload = 10 pF 1
(1) Specified by design.
(2) With internal reference powered down, REF_SEL = 1.