JAJSDX6A september   2017  – july 2023 ADS8588H

PRODUCTION DATA  

1.   1
2. 1 特長
3. 2 アプリケーション
4. 3 概要
5. 4 Revision History
6. 5 Pin Configuration and Functions
7. 6 Specifications
   1. 6.1  Absolute Maximum Ratings
   2. 6.2  ESD Ratings
   3. 6.3  Recommended Operating Conditions
   4. 6.4  Thermal Information
   5. 6.5  Electrical Characteristics
   6. 6.6  Timing Requirements: CONVST Control
   7. 6.7  Timing Requirements: Data Read Operation
   8. 6.8  Timing Requirements: Parallel Data Read Operation, CS and RD Tied Together
   9. 6.9  Timing Requirements: Parallel Data Read Operation, CS and RD Separate
   10. 6.10 Timing Requirements: Serial Data Read Operation
   11. 6.11 Timing Requirements: Byte Mode Data Read Operation
   12. 6.12 Timing Requirements: Oversampling Mode
   13. 6.13 Timing Requirements: Exit Standby Mode
   14. 6.14 Timing Requirements: Exit Shutdown Mode
   15. 6.15 Switching Characteristics: CONVST Control
   16. 6.16 Switching Characteristics: Parallel Data Read Operation, CS and RD Tied Together
   17. 6.17 Switching Characteristics: Parallel Data Read Operation, CS and RD Separate
   18. 6.18 Switching Characteristics: Serial Data Read Operation
   19. 6.19 Switching Characteristics: Byte Mode Data Read Operation
   20. 6.20 Timing Diagrams
   21. 6.21 Typical Characteristics
8. 7 Detailed Description
   1. 7.1 Overview
   2. 7.2 Functional Block Diagram
   3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Analog Input Impedance
      3. 7.3.3  Input Clamp Protection Circuit
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  Third-Order, Low-Pass Filter (LPF)
      6. 7.3.6  ADC Driver
      7. 7.3.7  Digital Filter and Noise
      8. 7.3.8  Reference
         1. 7.3.8.1 Internal Reference
         2. 7.3.8.2 External Reference
         3. 7.3.8.3 Supplying One VREF to Multiple Devices
      9. 7.3.9  ADC Transfer Function
      10. 7.3.10 ADS8588H Device Family Comparison
   4. 7.4 Device Functional Modes
      1. 7.4.1 Device Interface: Pin Description
         1. 7.4.1.1  REFSEL (Input)
         2. 7.4.1.2  RANGE (Input)
         3. 7.4.1.3  STBY (Input)
         4. 7.4.1.4  PAR/SER/BYTE SEL (Input)
         5. 7.4.1.5  CONVSTA, CONVSTB (Input)
         6. 7.4.1.6  RESET (Input)
         7. 7.4.1.7  RD/SCLK (Input)
         8. 7.4.1.8  CS (Input)
         9. 7.4.1.9  OS[2:0]
         10. 7.4.1.10 BUSY (Output)
         11. 7.4.1.11 FRSTDATA (Output)
         12. 7.4.1.12 DB15/BYTE SEL
         13. 7.4.1.13 DB14/HBEN
         14. 7.4.1.14 DB[13:9]
         15. 7.4.1.15 DB8/DOUTB
         16. 7.4.1.16 DB7/DOUTA
         17. 7.4.1.17 DB[6:0]
      2. 7.4.2 Device Modes of Operation
         1. 7.4.2.1 Power-Down Modes
            1. 7.4.2.1.1 Standby Mode
            2. 7.4.2.1.2 Shutdown Mode
         2. 7.4.2.2 Conversion Control
            1. 7.4.2.2.1 Simultaneous Sampling on All Input Channels
            2. 7.4.2.2.2 Simultaneous Sampling Two Sets of Input Channels
         3. 7.4.2.3 Data Read Operation
            1. 7.4.2.3.1 Parallel Data Read
            2. 7.4.2.3.2 Parallel Byte Data Read
            3. 7.4.2.3.3 Serial Data Read
            4. 7.4.2.3.4 Data Read During Conversion
         4. 7.4.2.4 Oversampling Mode of Operation
9. 8 Application and Implementation
   1. 8.1 Application Information
   2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
   3. 8.3 Power Supply Recommendations
   4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
       1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
11. 10Mechanical, Packaging, and Orderable Information