The ADS8588H supports a parallel byte interface mode for reading the device output data using the control inputs ( CS and RD), the parallel output bus (DB[15:0]), and the BUSY indicator. This interface mode is selected by applying a logic high input on the PAR/SER/BYTE SEL input pin and a logic high input on the DB15/BYTE SEL input pin. The parallel byte interface mode is very similar to the parallel interface mode, except that the output data for each channel is read in two data transfers of 8-bit byte sizes.

The order of most significant byte (MSB byte) and least significant byte (LSB byte) is decided by the logic input state of the DB14/HBEN pin. In parallel byte mode, the DB14/HBEN pin functions as a control input. When DB14/HBEN pin is tied high, the MSB byte of the conversion results is output first followed by the LSB byte. This order is reversed when DB14/HBEN is tied to logic low.

The Timing Requirements: Byte Mode Data Read Operation table describes the data read back operation during parallel byte mode when the DB14/HBEN pin is tied high. A falling edge of the CS input is used to activate the parallel bus, DB[7:0] for the device. The RD signal is then used to clock the conversion data out of the device. In this mode, two RD pulses are required to read the full data output for each analog channel. At the first falling edge of the RD signal, the first byte of the channel 1 conversion result becomes available on DB[7:0]. This byte is followed by the second byte of conversion data on the next falling edge of the RD signal. On subsequent falling edges of the RD signal, the output data for the remaining channels are clocked out in chunks of 8-bit bytes on DB[7:0] in a sequential manner. Thus, a total of 16 RD pulses are required to read the output from all input channels of the ADS8588H.

In this mode, the FRSTDATA output goes high at the first falling edge of the RD signal. FRSTDATA remains high for two RD pulses until both bytes of the channel 1 conversion result are output. At the third falling edge of the RD signal, the FRSTDATA output goes low and remains low throughout the data read operation until going to tri-state at the next rising edge of the CS signal.