JAJSDX6A september   2017  – july 2023 ADS8588H

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: CONVST Control
    7. 6.7  Timing Requirements: Data Read Operation
    8. 6.8  Timing Requirements: Parallel Data Read Operation, CS and RD Tied Together
    9. 6.9  Timing Requirements: Parallel Data Read Operation, CS and RD Separate
    10. 6.10 Timing Requirements: Serial Data Read Operation
    11. 6.11 Timing Requirements: Byte Mode Data Read Operation
    12. 6.12 Timing Requirements: Oversampling Mode
    13. 6.13 Timing Requirements: Exit Standby Mode
    14. 6.14 Timing Requirements: Exit Shutdown Mode
    15. 6.15 Switching Characteristics: CONVST Control
    16. 6.16 Switching Characteristics: Parallel Data Read Operation, CS and RD Tied Together
    17. 6.17 Switching Characteristics: Parallel Data Read Operation, CS and RD Separate
    18. 6.18 Switching Characteristics: Serial Data Read Operation
    19. 6.19 Switching Characteristics: Byte Mode Data Read Operation
    20. 6.20 Timing Diagrams
    21. 6.21 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Analog Input Impedance
      3. 7.3.3  Input Clamp Protection Circuit
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  Third-Order, Low-Pass Filter (LPF)
      6. 7.3.6  ADC Driver
      7. 7.3.7  Digital Filter and Noise
      8. 7.3.8  Reference
        1. 7.3.8.1 Internal Reference
        2. 7.3.8.2 External Reference
        3. 7.3.8.3 Supplying One VREF to Multiple Devices
      9. 7.3.9  ADC Transfer Function
      10. 7.3.10 ADS8588H Device Family Comparison
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Interface: Pin Description
        1. 7.4.1.1  REFSEL (Input)
        2. 7.4.1.2  RANGE (Input)
        3. 7.4.1.3  STBY (Input)
        4. 7.4.1.4  PAR/SER/BYTE SEL (Input)
        5. 7.4.1.5  CONVSTA, CONVSTB (Input)
        6. 7.4.1.6  RESET (Input)
        7. 7.4.1.7  RD/SCLK (Input)
        8. 7.4.1.8  CS (Input)
        9. 7.4.1.9  OS[2:0]
        10. 7.4.1.10 BUSY (Output)
        11. 7.4.1.11 FRSTDATA (Output)
        12. 7.4.1.12 DB15/BYTE SEL
        13. 7.4.1.13 DB14/HBEN
        14. 7.4.1.14 DB[13:9]
        15. 7.4.1.15 DB8/DOUTB
        16. 7.4.1.16 DB7/DOUTA
        17. 7.4.1.17 DB[6:0]
      2. 7.4.2 Device Modes of Operation
        1. 7.4.2.1 Power-Down Modes
          1. 7.4.2.1.1 Standby Mode
          2. 7.4.2.1.2 Shutdown Mode
        2. 7.4.2.2 Conversion Control
          1. 7.4.2.2.1 Simultaneous Sampling on All Input Channels
          2. 7.4.2.2.2 Simultaneous Sampling Two Sets of Input Channels
        3. 7.4.2.3 Data Read Operation
          1. 7.4.2.3.1 Parallel Data Read
          2. 7.4.2.3.2 Parallel Byte Data Read
          3. 7.4.2.3.3 Serial Data Read
          4. 7.4.2.3.4 Data Read During Conversion
        4. 7.4.2.4 Oversampling Mode of Operation
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Detailed Design Procedure

For the ADS8588H, each channel incorporates an analog front-end composed of a programmable gain amplifier (PGA), analog low-pass filter, and ADC input driver. The analog input for each channel presents a constant resistive impedance of 1 MΩ independent of the ADC sampling frequency and range setting. The high input impedance of the analog front-end circuit allows direct connection to potential transformers (PT) and current transformers (CT). The ADC inputs can support up to ±10-V or ± 5-V bipolar inputs and the integrated signal conditioning eliminates the need for external amplifiers or ADC driver circuits.

The PT and CT used in the system (Figure 8-1) have a ±10-V output range. Although the PT and CT provide isolation from the power system, a series resistor must be placed on the analog input channels. The series resistor helps limit the input current to ±10 mA if the input voltages exceed ±15 V. For applications that require protection against overvoltage or fast transient events beyond the specified absolute maximum ratings of the device, an external protection clamp circuit using transient voltage suppressors (TVS) and ESD diodes is recommended.

A low-pass filter is used on each analog input channel to eliminate high-frequency noise pickup and minimize aliasing. Figure 8-2 shows an example of the recommended configuration for an input RC filter. A balanced RC filter configuration matches the external source resistance on the positive path (AIN_nP) with an equal resistance on the negative path (AIN_nGND). Matching the source impedance in the positive and negative path allows for better common-mode noise rejection and helps maintain the dc accuracy of the system by canceling any additional offset error contributed by the external series resistance.

GUID-FFDC52DC-F907-487D-B5CA-72B5B495DE13-low.svgFigure 8-2 Input RC Low-Pass Filter

The primary goal of the data acquisition system illustrated in Figure 8-1 is to measure up to 20 harmonics in a 60-Hz power network. Thus, the analog front-end must have sufficient bandwidth to detect signals up to 1260 Hz, as shown in Equation 1.

Equation 1. GUID-808F16B3-9A41-4A8D-827B-B707D0B16741-low.gif

Based on the bandwidth calculated in Equation 1, the ADS8588H is set to simultaneously sample all eight channels at 20 kSPS, which is sufficient throughput to clearly resolve the highest harmonic component of the input signal. The pass band of the low-pass filter configuration shown in Figure 8-2 is determined by the –3-dB frequency, calculated according to Equation 2.

Equation 2. GUID-87106CF0-A074-4313-A501-5698FE443C81-low.gif

The value of CF is selected as 5.6 nF, a standard capacitance value available in 0603-size surface-mount components. In combination with the resistor RF, this low-pass filter provides sufficient bandwidth to accommodate the required 20 harmonics for the input signal of 60 Hz.

The ADS8588H can operate with either the internal voltage reference or an external reference. The Internal Reference section describes the electrical connections and recommended bypass capacitors when using the internal reference. Alternatively for applications that require a higher precision voltage reference, Figure 8-3 illustrates an example of an external reference circuit. The REF5025 provides a very low drift, and very accurate external 2.5-V reference. The resistor RFILT and capacitor CFILT form a low-pass filter to reduce the broadband noise and minimize the resulting effect of the reference noise on the system performance.

GUID-58977DFD-4816-4F9B-AA0E-A16BF63AB619-low.gifFigure 8-3 External Reference Circuit for the ADS8588H