The ADS8588H supports the oversampling mode of operation using an on-chip averaging digital filter, as explained in the Digital Filter and Noise section. The device can be configured in oversampling mode by the OS[2:0] pins (see the OS[2:0] section). Figure 7-20 shows a typical timing diagram for the oversampling mode of operation. The input on the OS pins is latched on the falling edge of the BUSY signal to configure the oversampling rate for the next conversion.

Figure 7-20 OSR Mode Operation Timing Diagram

In the oversampling mode of operation, both the CONVSTA and CONVSTB signals must be tied together or driven together. The BUSY signal width varies with the OSR setting because the conversion time increases with increase in OSR, as shown in Figure 7-20. The high time for the BUSY signal increases with the OSR setting, as listed in the Timing Requirements: CONVST ControlTiming Requirements: CONVST Control table.

For any particular OSR setting, the maximum achievable throughput per channel is specified in Table 7-1. If the application is running at a lower throughput, then a higher OSR setting can be selected for further noise reduction and SNR improvement. To maximize the throughput per channel, perform a data read when BUSY is high and a conversion is ongoing in OSR mode. This process enables data read for the previous conversion (see the Data Read During Conversion section). At the falling edge of the BUSY signal, the internal data registers are updated with the new conversion data; thus the read operation must complete and CS must be pulled high for at least t_{DZ_CSBSY} before BUSY goes low (see the Timing Requirements: Data Read OperationTiming Requirements: Data Read OperationTiming Requirements: Data Read Operation table).

Oversampling the input signal reduces noise during the conversion process, thus reducing the histogram code spread for a dc input signal to the ADC. Figure 7-21 to Figure 7-26 show the effect of oversampling on the output code spread in a dc histogram plot.

Mean = –0.22, sigma = 0.48

Figure 7-21 DC Histogram for OSR2

Mean = –0.49, sigma = 0.36

Figure 7-23 DC Histogram for OSR8

Mean = 0.13, sigma = 0.31

Figure 7-25 DC Histogram for OSR32

Mean = –0.43, sigma = 0.41

Figure 7-22 DC Histogram for OSR4

Mean = 0.49, sigma = 0.33

Figure 7-24 DC Histogram for OSR16

Mean = –0.21, sigma = 0.30

Figure 7-26 DC Histogram for OSR64

In OSR modes, the device adds a digital filter at the output of the ADC. The digital filter affects the frequency response of the entire data acquisition system including the internal low-pass analog filter and the oversampling digital filter. Figure 7-27 to Figure 7-32 show the frequency response curves for different OSR settings in the ±10-V range.

AVDD = 5 V, DVDD = 5 V, TA = 25°C, input range = ±10 V

Figure 7-27 Digital Filter Response for OSR = 2

AVDD = 5 V, DVDD = 5 V, TA = 25°C, input range = ±10 V

Figure 7-29 Digital Filter Response for OSR = 8

AVDD = 5 V, DVDD = 5 V, TA = 25°C, input range = ±10 V

Figure 7-31 Digital Filter Response for OSR = 32

AVDD = 5 V, DVDD = 5 V, TA = 25°C, input range = ±10 V

Figure 7-28 Digital Filter Response for OSR = 4

AVDD = 5 V, DVDD = 5 V, TA = 25°C, input range = ±10 V

Figure 7-30 Digital Filter Response for OSR = 16

AVDD = 5 V, DVDD = 5 V, TA = 25°C, input range = ±10 V

Figure 7-32 Digital Filter Response for OSR = 64