ADS8598S 18ビット、200kSPS、8チャネル同時サンプリング、単一電源の双極性入力対応ADC

Table 1. Oversampling Bit Decoding

7.3.8.1 Internal Reference

The device has an internal 2.5-V (nominal value) band-gap reference. In order to select the internal reference, the REFSEL pin must be tied high or connected to DVDD. When the internal reference is used, REFIN/REFOUT (pin 42) becomes an output pin with the internal reference value. A 10-μF (minimum) decoupling capacitor, as shown in Figure 57, is recommended to be placed between the REFIN/REFOUT pin and REFGND (pin 43). The capacitor must be placed as close to the REFIN/REFOUT pin as possible. The output impedance of the internal band-gap creates a low-pass filter with this capacitor to band-limit the noise of the band-gap output. The use of a smaller capacitor increases the reference noise in the system, thus degrading SNR and SINAD performance. Do not use the REFIN/REFOUT pin to drive external ac or dc loads because of the limited current output capability of the pin. The REFIN/REFOUT pin can be used as a reference source if followed by a suitable op amp buffer.

Figure 57. Device Connections for Using an Internal 2.5-V Reference

The device internal reference is factory trimmed to a maximum initial accuracy of ±2.5 mV. The histogram in Figure 58 shows the distribution of the internal voltage reference output taken from more than 2100 devices.

Figure 58. Internal Reference Accuracy at Room Temperature Histogram

The initial accuracy specification for the internal reference can be degraded if the die is exposed to any mechanical, thermal, or environmental stress (such as humidity). Heating the device when being soldered to a printed circuit board (PCB) and any subsequent solder reflow is a primary cause for shifts in the V_REF value. The main cause of thermal hysteresis is a change in die stress and therefore is a function of the package, die-attach material, and molding compound, as well as the layout of the device itself.

In order to illustrate this effect, 80 devices were soldered using lead-free solder paste with the suggested manufacturer reflow profile, as explained in the AN-2029 Handling & Process Recommendations application report. The internal voltage reference output is measured before and after the reflow process and Figure 59 shows the typical shift in value. Although all tested units exhibit a positive shift in the output voltages, negative shifts are also possible. The histogram in Figure 59 shows the typical shift for exposure to a single reflow profile. Exposure to multiple reflows, which is common on PCBs with surface-mount components on both sides, causes additional shifts in the output voltage. If the PCB is to be exposed to multiple reflows, solder the ADS8598S in the last pass to minimize device exposure to thermal stress.

Figure 59. Solder Heat Shift Distribution Histogram

The internal reference is also temperature compensated to provide excellent temperature drift over an extended industrial temperature range of –40°C to +125°C. Figure 60 shows the variation of the internal reference voltage across temperature for different values of the AVDD supply voltage. The typical specified value of the reference voltage drift over temperature is 7.5 ppm/°C.

Figure 60. Variation of Internal Reference Output (REFIN/REFOUT) vs Free-Air Temperature and Supply

7.3.8.2 External Reference

For applications that require a reference voltage with lower temperature drift or a common reference voltage for multiple devices, the ADS8598S offers a provision to use an external reference, using the internal buffer to drive the ADC reference pin. In order to select the external reference mode, either tie the REFSEL pin low or connect this pin to AGND. In this mode, an external 2.5-V reference must be applied at REFIN/REFOUT (pin 42), which becomes a high-impedance input pin. Any low-drift, small-size external reference can be used in this mode because the internal buffer is optimally designed to handle the dynamic loading on the ADC reference input. The output of the external reference must be filtered to minimize the resulting effect of the reference noise on system performance. Figure 61 illustrates a typical connection diagram for this mode.

Figure 61. Device Connections for Using an External 2.5-V Reference

For closed-loop operation of the internal reference buffer, the REFCAPA and REFCAPB pins must be externally shorted together. The output of the internal reference buffer appears at the REFCAP pin. A minimum capacitance of 10 µF must be placed between the REFCAPA, REFCAPB pins and REFGND (pin 43). Place this capacitor as close as possible to the REFCAPA and REFCAPB pins. Do not use this internal reference buffer to drive external ac or dc loads because of the limited current output capability.

Figure 62 shows that the performance of the internal buffer output is very stable across the entire operating temperature range of –40°C to +125°C. Figure 63 shows that the typical specified value of the reference buffer drift over temperature is 5 ppm/°C.

Figure 62. Variation of Reference Buffer Output (REFCAPA, REFCAPB) vs Free-Air Temperature and Supply

Number of samples = 30

Figure 63. Reference Buffer Temperature Drift Histogram

7.3.8.3 Supplying One V_REF to Multiple Devices

For applications that require multiple ADS8598S devices, using the same reference voltage source for all ADCs helps eliminate any potential errors in the system resulting from mismatch between multiple reference sources.

Figure 64 illustrates the recommended connection diagram for an application that uses one device in internal reference mode and provides the reference source for other devices. The device used as source of the voltage reference is bypassed by a 10-µF capacitor on the REFIN/REFOUT pin, whereas the other devices are bypassed with a 100-nF capacitor.

Figure 64. Multiple Devices Connected With an Internal Reference From one Device

Figure 65 shows the recommended connection diagram for an application that uses an external voltage reference (such as the REF5025) to provide the reference source for multiple devices.

Figure 65. Multiple Devices Connected Using an External Reference

Table 2. ADC LSB Values for Different Input Ranges

Table 3. Device Family Comparison

7.4.1.1 REFSEL (Input)

The REFSEL pin is a digital input pin that enables selection between the internal and external reference mode of operation for the device. If the REFSEL pin is set to logic high, then the internal reference is enabled and selected. If this pin is set to logic low, then the internal band-gap reference circuit is disabled and powered down. In this mode, an external reference voltage must be provided to the REFIN/REFOUT pin. Under both conditions, the internal reference buffer is always enabled.

The REFSEL pin is an asynchronous logic input. The device output on the REFIN/REFOUT pin starts changing immediately with a change in state of the REFSEL input pin. During power-up, the device wakes up in internal or external reference mode depending on the state of the REFSEL input pin.

7.4.1.2 RANGE (Input)

The RANGE pin is a digital input pin that allows the input range to be selected for all analog input channels. If this pin is set to logic high, the device is configured to operate in the ±10-V input range for all input channels. If this pin is set to logic low, then all input channels operate in the ±5-V input range.

In applications where the input range remains the same for all input channels, the RANGE pin is recommended to be hardwired to the appropriate signal. However, some applications can require an on-the-fly change in the input range by the digital host. For such cases, the RANGE pin functions as an asynchronous input, meaning that any change in the logic input results in an immediate change in the input range configuration of the device. An additional 80 µs must typically be allowed in addition to the device acquisition time for the internal active circuitry to settle to the required accuracy before initiating the next conversion.

The RANGE pin is also used to put the device in standby or shutdown mode depending on the state of the STBY input pin, as explained in the Power-Down Modes section.

7.4.1.3 STBY (Input)

The STBY pin is a digital input pin used to put the device into one of the two power-down modes: standby and shut down. Set the STBY pin to logic high for normal device operation. If this pin is set to logic low, the device enters either standby mode or shutdown mode depending on the state of the RANGE input pin. Both of these modes are low-power modes supported by the device. In shutdown mode, all internal circuitry is powered down, but in standby mode the internal reference and regulators remain powered to enable a relatively quicker recovery to normal operation.

The STBY pin functions as an asynchronous input, meaning that this pin can be pulled low at anytime during device operation to put the device into one of the two power-down modes. However, if the STBY input is set high to bring the device out of power-down mode, then wait for the specified recovery time, as specified in the Timing Requirements: Exit Standby Mode table for proper operation. See the Power-Down Modes section for more details on device operation in the two power-down modes.

7.4.1.4 PAR/SER/BYTE SEL (Input)

The PAR/SER/BYTE SEL pin is a digital input pin that selects between the parallel, serial, or parallel byte interface for reading the data output from the device. If this pin is tied to logic low, then the device operates in the parallel interface mode (see the Parallel Data Read section). If this pin is tied to logic high, then the serial or parallel byte interface mode is selected depending on the state of the DB15/BYTE SEL pin. If the DB15/BYTE SEL is tied low, then serial mode is selected (see the Serial Data Read section) and the parallel byte interface is selected if this pin is tied high (see the Parallel Byte Data Read section).

7.4.1.5 CONVSTA, CONVSTB (Input)

Conversion start A (CONVSTA) and conversion start B (CONVSTB) are active-high, conversion control digital input signals. CONVSTA can be used to simultaneously sample and initiate the conversion process for the first half count of device input channels (channels 1-4), whereas CONVSTB can be used to simultaneously sample and initiate the conversion process for the latter half count of device input channels (channels 5-8). For simultaneous sampling of all input channels, both pins can be shorted together and a single CONVST signal can be used to control the conversion on all input channels. However, in the oversampling mode of operation (see the Oversampling Mode of Operation section), both the CONVSTA and CONVSTB signals must be tied together.

On the rising edge of the CONVSTA, CONVSTB signals, the internal track-and-hold circuits for each analog input channel are placed into hold mode and the sampled input signal is converted using an internal clock. The CONVSTA, CONVSTB signals can be pulled low when the internal conversion is over, as indicated by the BUSY signal (see the BUSY (Output) section). At this point, the front-end circuit for all analog input channels acquire the respective input signals and the internal ADC is not converting. The output data can be read from the device irrespective of the status of the CONVSTA, CONVSTB pins, as there is no degradation in device performance, as explained in the Data Read Operation section.

7.4.1.6 RESET (Input)

The RESET pin is an active-high digital input. A dedicated reset pin allows the device to be reset at any time in an asynchronous manner. All digital circuitry in the device is reset when the RESET pin is set to logic high and this condition remains active until the pin returns low. The device must always be reset after power-up as well as after recovery from shut-down mode when all supplies and references have settled to the required accuracy. If the RESET is issued during an ongoing conversion process, then the device aborts the conversion and output data are invalid. If the reset signal is applied during a data read operation, then the output data registers are all reset to zero.

In order to initiate the next conversion cycle after deactivating a reset condition, allow for a minimum time delay between the falling edge of the RESET input and the rising edge of the CONVSTA, CONVSTB inputs (see the Timing Requirements: CONVST Control table). Any violation in this timing requirement can result in corrupting the results from the next conversion.

7.4.1.7 RD/SCLK (Input)

RD/SCLK is a dual-function pin. Table 4 explains the usage of this pin under different operating conditions of the device.

7.4.1.8 CS (Input)

The CS pin indicates an active-low, chip-select signal. A rising edge on the CS signal configures all data lines in tri-state mode. This function allows multiple devices to share the same output data lines. The falling edge of the CS signal marks the beginning of the output data transfer frame in any interface mode of operation for the device. In the parallel and parallel byte interface modes, both the CS and RD input pins must be driven low to enable the digital output bus for reading the conversion data (DB[15:0] for parallel and DB[7:0] for parallel byte interface). In serial mode, the falling edge of the CS signal takes the DOUTA, DOUTB serial data output lines out of tri-state mode and outputs the MSB of the previous conversion result.

7.4.1.9 OS[2:0]

The OS[2:0] pins are active-high digital input pins used to configure the oversampling ratio for the internal digital filter on the device. OS2 is the MSB control bit and OS0 is the LSB control bit. Table 1 provides the decoding of the OS[2:0] bits for different oversampling rates. As described in Table 1, an increase in the OSR mode improves the typical SNR performance for both input ranges and reduces the 3-dB input bandwidth as well as the maximum-allowed throughput per channel.

7.4.1.10 BUSY (Output)

BUSY is an active-high digital output signal. This pin goes to logic high after the rising edges of both the CONVSTA and CONVSTB signals, indicating that the front-end, track-and-hold circuits for all input channels are in hold mode and that the ADC conversion has started. When the BUSY signal goes high, any activity on the CONVSTA or CONVSTB inputs has no effect on the device. The BUSY output remains high until the conversion process for all channels is completed and the conversion data are latched into the output data registers for read out. If the conversion data are read for the previous conversion when BUSY is high, ensure that the data read operation is complete before the falling edge of the BUSY output.

7.4.1.11 FRSTDATA (Output)

FRSTDATA is an active-high digital output signal that indicates if the conversion data output for the first analog input channel of the ADC (AIN_1P and AIN_1GND) is being read out in either of the interface modes. The FRSTDATA output pin comes out of tri-state when the CS input is pulled from a high to a low logic level. Table 5 indicates the functionality of the FRSTDATA output in different interface modes of the device.

7.4.1.12 DB15/BYTE SEL

DB15/BYTE SEL is a dual-function, digital input, output pin.

When the device operates in parallel interface mode (PAR/SER/BYTE SEL = 0), this pin functions as a digital output. In this mode, this pin is active when the CS signal is pulled low. This pin outputs bit 17 of the conversion result during the first RD pulse and bit 1 of the same conversion result during the second RD pulse.

When the device does not operate in parallel interface mode (PAR/SER/BYTE SEL = 1), this pin functions as a digital control input pin to select between the serial and parallel byte interface modes. The device operates in the serial interface mode when the DB15/BYTE SEL pin is tied low and the device operates in the parallel byte interface mode when this pin is tied to a logic high input.

7.4.1.13 DB14/HBEN

DB14/HBEN is a dual-function, digital input, output pin.

When the device operates in parallel interface mode (PAR/SER/BYTE SEL = 0), this pin functions as a digital output. In this mode, this pin is active when the CS signal is pulled low. This pin outputs bit 16 of the conversion result during the first RD pulse and bit 0 of the same conversion result during the second RD pulse.

When the device operates in parallel byte interface mode (PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1), this pin functions as a digital control input pin that selects if the MSB byte or the LSB byte is output first. If the DB14/HBEN pin is tied to logic high, then the MSB byte (bit[17:10]) is output first followed by the mid byte (bit[9:2]) followed by the LSB byte (bit[1:0] and six zeros) and vice-versa if this pin is tied to logic low.

When the device operates in serial interface mode (PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 0), this pin must be tied to AGND or to a logic low input.

7.4.1.14 DB[13:9]

DB[13:9] are digital output pins. In parallel interface mode (PAR/SER/BYTE SEL = 0), these pins output bit 15 to bit 11 of the conversion result for each analog channel when both the CS and RD signals are pulled low. When the device is not in parallel interface mode (PAR/SER/BYTE SEL = 1), these pins must be tied to AGND or to a logic low input.

7.4.1.15 DB8/DOUTB

DB8/DOUTB is a dual-function digital output pin.

In parallel interface mode (PAR/SER/BYTE SEL = 0), use this pin to output bit 10 of the conversion result followed by a zero for each analog channel when both the CS and RD signals are pulled low.

When the device operates in parallel byte interface mode (PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1), this pin remains in a tri-state mode.

In serial interface mode (PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 0), this pin outputs the conversion data for the second half count of device input channels (channels 5-8).

7.4.1.16 DB7/DOUTA

DB7/DOUTA is a dual-function digital output pin.

In parallel interface mode (PAR/SER/BYTE SEL = 0), use this pin to output bit 9 of the conversion result followed by a zero for each analog channel when both the CS and RD signals are pulled low.

When the device operates in parallel byte interface mode (PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1), this pin outputs the MSB of the output byte of the conversion data.

In serial interface mode (PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 0), use this pin to output conversion data for the first half count of device input channels (channels 1-4).

7.4.1.17 DB[6:0]

DB[6:0] are digital output pins.

In parallel interface mode (PAR/SER/BYTE SEL = 0), these pins output bit 8 to bit 2 of the conversion result followed by a zero for each analog channel when both the CS and RD signals are pulled low.

When the device operates in parallel byte interface mode (PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1), these pins along with the DB7 pin output the 18-bit conversion result in MSB-first fashion in three consecutive RD operations.

When the device operates in serial interface mode (PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 0), these pins must be tied to AGND or to a logic low input.

7.4.2.1 Power-Down Modes

For applications that are sensitive to power consumption, the ADS8598S offers a built-in, power-down feature. The device supports two power-down modes: standby mode and shutdown mode. As shown in Table 6, the device can enter either power-down mode by pulling the STBY pin to a logic low level. Additionally, the selection between these two power-down modes is done by the state of the RANGE pin.

7.4.2.2 Conversion Control

The ADS8598S offers easy and precise control to simultaneously sample all analog input channels or pairs of input channels. The sampling instant can be user-controlled through the digital pins, CONVSTA and CONVSTB. Simultaneously capturing the input signal on all analog input channels is extremely useful in certain applications that are sensitive to additional phase delay between input channels caused by sequential sampling. This section describes the methodology to simultaneously sample all input channels or pairs of input channels for the device.

7.4.2.2.1 Simultaneous Sampling on All Input Channels

The ADS8598S allows all the analog input channels to be simultaneously sampled. In order to do so, the CONVSTA and CONVSTB signals must be tied together (see Figure 67) and a single CONVST signal must be used to control the sampling of all analog input channels of the device. Figure 67 also provides the sequence of events described in this section.

Figure 67. Simultaneous Sampling of All Input Channels in Parallel Interface Timing Diagram

There are four events that describe the internal operation of the device when all input channels are simultaneously sampled and the data are read back. These events are:

• Event 1: Simultaneous sampling of all analog input channels is initiated with the rising edge of the CONVST signal. The input signals on all channels are sampled at this same instant because both the CONVSTA and CONVSTB inputs are tied together. The sampled signals are then converted by the ADC using a precise on-chip oscillator clock. At the beginning of the conversion phase of the ADC, the BUSY output goes high and remains high through a maximum-specified conversion time of t_CONV (see the Timing Requirements: CONVST Control table).
• Event 2: At this instant, the ADC has completed the conversion for all input channels and the BUSY output goes to logic low. The falling edge of the BUSY signal indicates the end of conversion and that the internal registers are updated with the conversion data. At this instant, the device is ready to output the correct conversion results for all channels on the parallel output bus (DB[15:0]), or serial output lines (DOUTA, DOUTB), or parallel byte bus (DB[7:0]).
• Event 3: This example shows the data read operation in parallel interface mode with both CS and RD tied together. After BUSY goes low, the first falling edges of CS and RD output the most significant 16 bits conversion result of channel 1 (AIN_1) on the parallel output bus. The next falling edges of CS and RD output the two least significant bits on DB1 and DB0 respectively. Similarly, the conversion results for the remaining channels are output on the parallel bus on subsequent falling edges of the CS and RD signals in a sequential manner. If all channels are not used in the conversion process, tie the unused channels to AGND or any known voltage within the selected input range. The ADC always converts all analog input channels and the results for unused channels are included in the output data stream, thus all unused channels must be tied to AGND or known voltage within the range. The FRSTDATA output goes high on the first falling edges of the CS and RD signals, indicating that the parallel bus is carrying the output result from channel 1. The FRSTDATA output stays high until the AIN_1 data output is read out. On the next falling edges of the CS and RD signals, FRSTDATA goes low and stays low if the CS and RD inputs are low.
• Event 4: After the conversion results for all analog channels are output from the device, the data frame can be terminated by pulling the CS and RD signals to logic high. The parallel bus and FRSTDATA output go to tri-state until the entire sequence is repeated beginning from event 1.

Events 1 and 2 are common to all interface modes of operation (parallel or serial or parallel byte).

7.4.2.2.2 Simultaneous Sampling Two Sets of Input Channels

The ADS8598S allows two sets of analog input channels to be simultaneously sampled. In order to do so, the CONVSTA and CONVSTB signals must be separate control inputs (as shown in Figure 68) and the device must not operate in any oversampling mode. Electrical grid relay protection is an application that can benefit from being able to sample the inputs in two groups. The delay of the signal through the voltage channels is often different from the delay on the channels measuring current. The difference in delay created by the voltage and current signal paths can be corrected by adjusting the sampling of the two groups of inputs (voltage and current) to the device.

The timing diagram of Figure 68 shows the sequence of events described in this section.

Figure 68. Simultaneous Sampling of All Input Channels in Parallel Interface Timing Diagram

There are four events that describe the internal operation of the device when pairs of input channels are simultaneously sampled and the data are read back. These events are:

• Event 1(a): A rising edge on the CONVSTA signal initiates simultaneous sampling of the first set of analog input channels (channels 1-4). The sampling circuits on the first set of analog input channels enter hold mode and the input signals on these channels are sampled at the same instant. The ADC does not begin conversion until the input signals on the second set of channels are sampled.
• Event 1(b): A rising edge on the CONVSTB signal initiates simultaneous sampling of the second set of analog input channels (channels 5-8). The sampling circuits for the second set of analog input channels enter hold mode and the input signals on these channels are sampled at the same instant. When the rising edges of both the CONVSTA and CONVSTB signals have occurred, the ADC converts all sampled signals using a precise, on-chip oscillator clock. At the beginning of the conversion phase of the ADC, the BUSY output goes high and remains high through a maximum-specified conversion time of t_CONV (see the Timing Requirements: CONVST Control table).
• Event 2: Same as event 2 in the Simultaneous Sampling on All Input Channels section.
• Event 3: Same as event 3 in the Simultaneous Sampling on All Input Channels section.
• Event 4: Same as event 4 in the Simultaneous Sampling on All Input Channels section.

Events 1(a), 1(b), and 2 are common to all interface modes of operation (parallel, serial, or parallel byte).

7.4.2.3 Data Read Operation

The ADS8598S updates the internal data registers with the conversion data for all analog channels at the end of every conversion phase (when BUSY goes low). As described in the Timing Requirements: Data Read Operation table, if the output data are read after BUSY goes low, then the device outputs the conversion results for the current sample. However, if the output data are read when BUSY is high, then the device outputs conversion results for the previous sample. Under both conditions, the device supports three interface options as explained in Table 7 depending on the status of the PAR/SER/BYTE SEL and DB15/BYTE SEL pins.

7.4.2.4 Oversampling Mode of Operation

The ADS8598S supports the oversampling mode of operation using an on-chip averaging digital filter, as explained in the Digital Filter and Noise section. The device can be configured in oversampling mode by the OS[2:0] pins (see the OS[2:0] section). Figure 71 shows a typical timing diagram for the oversampling mode of operation. The input on the OS pins is latched on the falling edge of the BUSY signal to configure the oversampling rate for the next conversion.

Figure 71. OSR Mode Operation Timing Diagram

In the oversampling mode of operation, both the CONVSTA and CONVSTB signals must be tied together or driven together. As shown in Figure 71, the BUSY signal duration varies with the OSR setting because the conversion time increases with increases in OSR. The high time for the BUSY signal increases with the OSR setting, as listed in the Timing Requirements: CONVST Control table.

For any particular OSR setting, the maximum achievable throughput per channel is specified in Table 1. If the application is running at a lower throughput, then a higher OSR setting can be selected for further noise reduction and SNR improvement. To maximize the throughput per channel, perform a data read when BUSY is high and a conversion is ongoing in OSR mode. This process enables data read for the previous conversion (see the Data Read During Conversion section). At the falling edge of the BUSY signal, the internal data registers are updated with the new conversion data; thus the read operation must complete and CS must be pulled high for at least t_{DZ_CSBSY} before BUSY goes low (see the Timing Requirements: Data Read Operation table).

Oversampling the input signal reduces noise during the conversion process, thus reducing the histogram code spread for a dc input signal to the ADC. Figure 72 to Figure 77 show the effect of oversampling on the output code spread in a dc histogram plot.

Mean = 0.03, sigma = 1.52

Figure 72. DC Histogram for OSR2

Mean = –0.25, sigma = 1.09

Figure 74. DC Histogram for OSR8

Mean = –0.44, sigma = 0.75

Figure 76. DC Histogram for OSR32

Mean = –0.33, sigma = 1.39

Figure 73. DC Histogram for OSR4

Mean = –0.33, sigma = 0.89

Figure 75. DC Histogram for OSR16

Mean = –0.02, sigma = 0.72

Figure 77. DC Histogram for OSR64

In OSR modes, the device adds a digital filter at the output of the ADC. The digital filter affects the frequency response of the entire data acquisition system including the internal low-pass analog filter and the oversampling digital filter. Figure 78 to Figure 83 show the frequency response curves for different OSR settings in the ±10-V range.

AVDD = 5 V, DVDD = 5 V, TA = 25°C, input range = ±10 V

Figure 78. Digital Filter Response for OSR = 2

AVDD = 5 V, DVDD = 5 V, TA = 25°C, input range = ±10 V

Figure 80. Digital Filter Response for OSR = 8

AVDD = 5 V, DVDD = 5 V, TA = 25°C, input range = ±10 V

Figure 82. Digital Filter Response for OSR = 32

AVDD = 5 V, DVDD = 5 V, TA = 25°C, input range = ±10 V

Figure 79. Digital Filter Response for OSR = 4

AVDD = 5 V, DVDD = 5 V, TA = 25°C, input range = ±10 V

Figure 81. Digital Filter Response for OSR = 16

AVDD = 5 V, DVDD = 5 V, TA = 25°C, input range = ±10 V

Figure 83. Digital Filter Response for OSR = 64

8.2.1.1 Design Requirements

To begin the design process, a few parameters must be decided upon. The designer must know the following:

• Output range of the potential transformers (elements labeled PT in Figure 84)
• Output range of the current transformers (elements labeled CT in Figure 84)
• Input impedance required from the analog front-end for each channel
• Fundamental frequency of the power system
• Number of harmonics that must be acquired
• Type of signal conditioning required from the analog front-end for each channel

8.2.1.2 Detailed Design Procedure

For the ADS8598S, each channel incorporates an analog front-end composed of a programmable gain amplifier (PGA), analog low-pass filter, and ADC input driver. The analog input for each channel presents a constant resistive impedance of 1 MΩ independent of the ADC sampling frequency and range setting. The high input impedance of the analog front-end circuit allows direct connection to potential transformers (PT) and current transformers (CT). The ADC inputs can support up to ±10-V or ± 5-V bipolar inputs and the integrated signal conditioning eliminates the need for external amplifiers or ADC driver circuits.

The PT and CT used in the system, as illustrated in Figure 84, have a ±10-V output range. Although PT and CT provide isolation from the power system, a series resistor must be placed on the analog input channels. The series resistor helps limit the input current to ±10 mA if the input voltages exceed ±15 V. For applications that require protection against overvoltage or fast transient events beyond the specified absolute maximum ratings of the device, an external protection clamp circuit using transient voltage suppressors (TVS) and ESD diodes is recommended.

A low-pass filter is used on each analog input channel to eliminate high-frequency noise pickup and minimize aliasing. Figure 85 shows an example of the recommended configuration for an input RC filter. A balanced RC filter configuration matches the external source resistance on the positive path (AIN_nP) with an equal resistance on the negative path (AIN_nGND). Matching the source impedance in the positive and negative path allows for better common-mode noise rejection and helps maintain the dc accuracy of the system by canceling any additional offset error contributed by the external series resistance.

Figure 85. Input RC Low-Pass Filter

The primary goal of the data acquisition system illustrated in Figure 84 is to measure up to 20 harmonics in a 60-Hz power network. Thus, the analog front-end must have sufficient bandwidth (as shown in Equation 1) to detect signals up to 1260 Hz.

Equation 1.

Based on the bandwidth calculated in Equation 1, the ADS8598S is set to simultaneously sample all eight channels at 20 kSPS, which is sufficient throughput to clearly resolve the highest harmonic component of the input signal. The pass band of the low-pass filter configuration illustrated in Figure 85 is determined by the –3-dB frequency, calculated according to Equation 2.

Equation 2.

The value of C_F is selected as 5.6 nF, a standard capacitance value available in 0603-size surface-mount components. In combination with the resistor R_F, this low-pass filter provides sufficient bandwidth to accommodate the required 20 harmonics for the input signal of 60 Hz.

The ADS8598S can operate with either the internal voltage reference or an external reference. The Internal Reference section describes the electrical connections and recommended bypass capacitors when using the internal reference. Alternatively for applications that require a higher precision voltage reference, Figure 86 shows an example of an external reference circuit. The REF5025 provides a very low drift, and very accurate external 2.5-V reference. The resistor R_FILT and capacitor C_FILT form a low-pass filter to reduce the broadband noise and minimize the resulting effect of the reference noise on the system performance.

Figure 86. External Reference Circuit for the ADS8598S

8.2.1.3 Application Curve

Figure 87 shows the frequency spectrum of the data acquired by the ADS8598S for a sinusoidal, ±10-V input at 60 Hz.

The ac performance parameters measured by this design are:

• SNR = 93.95 dB; SINAD = 93.75 dB
• THD = –105 dB; SFDR = 108.7 dB

Figure 87. Frequency Spectrum for a Sinusoidal ±10-V Signal at 50 Hz

8.2.2.1 Design Requirements

To begin the design process, a few parameters must be decided upon. The designer must know the following:

• Input range of the signal
• Allowed error in the measured output

8.2.2.2 Detailed Design Procedure

For the ADS8598S, each channel incorporates an analog front-end with a constant resistive input impedance of 1 MΩ. The input resistance is independent of the PGA range selection or ADC sampling frequency. The input impedance along with the feedback resistance of the programmable gain amplifier (PGA) help achieve the required attenuation for the input high voltage signal to feed the ADC inputs.

As illustrated in Figure 88, a series resistance can be added to the AIN_nP and AIN_nGND pins. As shown in Equation 3, this series resistance increases the input impedance. When using high values of series resistances, avoid using a parallel capacitor between the AIN_nP and AIN-nGND pins. The leakage current of the capacitor introduces additional gain error.

Equation 3.

The increased series resistance along with the PGA feedback resistance increases the attenuation offered by the PGA, thus increasing the allowed input voltage range. Equation 4 calculates the increased input voltage range. Conversely, Equation 5 can be used to calculate the value of series resistance R_S based on the required input voltage range.

Equation 4.

Equation 5.

The additional series resistance introduces gain error in the system because the external resistors have mismatch and are not matched to the internal impedance of the ADC. Thus, high-accuracy, low-drift external resistors must be used. The gain error resulting from mismatch in external resistor and internal resistor must be calibrated to achieve the required accuracy levels.