8.2.1.1 Design Requirements

To begin the design process, a few parameters must be decided upon. The designer must know the following:

• Output range of the potential transformers (elements labeled PT in Figure 84)
• Output range of the current transformers (elements labeled CT in Figure 84)
• Input impedance required from the analog front-end for each channel
• Fundamental frequency of the power system
• Number of harmonics that must be acquired
• Type of signal conditioning required from the analog front-end for each channel

8.2.1.2 Detailed Design Procedure

For the ADS8598S, each channel incorporates an analog front-end composed of a programmable gain amplifier (PGA), analog low-pass filter, and ADC input driver. The analog input for each channel presents a constant resistive impedance of 1 MΩ independent of the ADC sampling frequency and range setting. The high input impedance of the analog front-end circuit allows direct connection to potential transformers (PT) and current transformers (CT). The ADC inputs can support up to ±10-V or ± 5-V bipolar inputs and the integrated signal conditioning eliminates the need for external amplifiers or ADC driver circuits.

The PT and CT used in the system, as illustrated in Figure 84, have a ±10-V output range. Although PT and CT provide isolation from the power system, a series resistor must be placed on the analog input channels. The series resistor helps limit the input current to ±10 mA if the input voltages exceed ±15 V. For applications that require protection against overvoltage or fast transient events beyond the specified absolute maximum ratings of the device, an external protection clamp circuit using transient voltage suppressors (TVS) and ESD diodes is recommended.

A low-pass filter is used on each analog input channel to eliminate high-frequency noise pickup and minimize aliasing. Figure 85 shows an example of the recommended configuration for an input RC filter. A balanced RC filter configuration matches the external source resistance on the positive path (AIN_nP) with an equal resistance on the negative path (AIN_nGND). Matching the source impedance in the positive and negative path allows for better common-mode noise rejection and helps maintain the dc accuracy of the system by canceling any additional offset error contributed by the external series resistance.

Figure 85. Input RC Low-Pass Filter

The primary goal of the data acquisition system illustrated in Figure 84 is to measure up to 20 harmonics in a 60-Hz power network. Thus, the analog front-end must have sufficient bandwidth (as shown in Equation 1) to detect signals up to 1260 Hz.

Equation 1.

Based on the bandwidth calculated in Equation 1, the ADS8598S is set to simultaneously sample all eight channels at 20 kSPS, which is sufficient throughput to clearly resolve the highest harmonic component of the input signal. The pass band of the low-pass filter configuration illustrated in Figure 85 is determined by the –3-dB frequency, calculated according to Equation 2.

Equation 2.

The value of C_F is selected as 5.6 nF, a standard capacitance value available in 0603-size surface-mount components. In combination with the resistor R_F, this low-pass filter provides sufficient bandwidth to accommodate the required 20 harmonics for the input signal of 60 Hz.

The ADS8598S can operate with either the internal voltage reference or an external reference. The Internal Reference section describes the electrical connections and recommended bypass capacitors when using the internal reference. Alternatively for applications that require a higher precision voltage reference, Figure 86 shows an example of an external reference circuit. The REF5025 provides a very low drift, and very accurate external 2.5-V reference. The resistor R_FILT and capacitor C_FILT form a low-pass filter to reduce the broadband noise and minimize the resulting effect of the reference noise on the system performance.

Figure 86. External Reference Circuit for the ADS8598S

8.2.1.3 Application Curve

Figure 87 shows the frequency spectrum of the data acquired by the ADS8598S for a sinusoidal, ±10-V input at 60 Hz.

The ac performance parameters measured by this design are:

• SNR = 93.95 dB; SINAD = 93.75 dB
• THD = –105 dB; SFDR = 108.7 dB

Figure 87. Frequency Spectrum for a Sinusoidal ±10-V Signal at 50 Hz

8.2.2.1 Design Requirements

To begin the design process, a few parameters must be decided upon. The designer must know the following:

• Input range of the signal
• Allowed error in the measured output

8.2.2.2 Detailed Design Procedure

For the ADS8598S, each channel incorporates an analog front-end with a constant resistive input impedance of 1 MΩ. The input resistance is independent of the PGA range selection or ADC sampling frequency. The input impedance along with the feedback resistance of the programmable gain amplifier (PGA) help achieve the required attenuation for the input high voltage signal to feed the ADC inputs.

As illustrated in Figure 88, a series resistance can be added to the AIN_nP and AIN_nGND pins. As shown in Equation 3, this series resistance increases the input impedance. When using high values of series resistances, avoid using a parallel capacitor between the AIN_nP and AIN-nGND pins. The leakage current of the capacitor introduces additional gain error.

Equation 3.

The increased series resistance along with the PGA feedback resistance increases the attenuation offered by the PGA, thus increasing the allowed input voltage range. Equation 4 calculates the increased input voltage range. Conversely, Equation 5 can be used to calculate the value of series resistance R_S based on the required input voltage range.

Equation 4.

Equation 5.

The additional series resistance introduces gain error in the system because the external resistors have mismatch and are not matched to the internal impedance of the ADC. Thus, high-accuracy, low-drift external resistors must be used. The gain error resulting from mismatch in external resistor and internal resistor must be calibrated to achieve the required accuracy levels.