A data transfer frame between the device and the host controller begins at the falling edge of the CONVST/CS pin and ends when the device starts conversion at the subsequent rising edge. The host controller can initiate a data transfer frame by bringing the CONVST/CS signal low (as shown in Figure 7-25) after the end of the CONV phase, as described in the CONV State section.

Figure 7-25 Data Transfer Frame

For a typical data transfer frame F:

1. The host controller pulls CONVST/CS low to initiate a data transfer frame. On the falling edge of the CONVST/CS signal:
   • RVS goes low, indicating the beginning of the data transfer frame.
   • The internal SCLK counter is reset to 0.
   • The device takes control of the data bus. As illustrated in Figure 7-25, the contents of the output data word are loaded into the 32-bit output shift register (OSR).
   • The internal configuration register is reset to 0000h, corresponding to a NOP command.
2. During the frame, the host controller provides clocks on the SCLK pin:
   • On each SCLK capture edge, the SCLK counter is incremented and the data bit received on the SDI pin is shifted into the LSB of the input shift register.
   • On each launch edge of the output clock (SCLK in this case), the MSB of the output shift register data is shifted out on the selected SDO-x pins.
   • The status of the RVS pin depends on the output protocol selection (see the Protocols for Reading From the Device section).
3. The host controller pulls the CONVST/CS pin high to end the data transfer frame. On the rising edge of CONVST/CS:
   • The SDO-x pins go to tri-state.
   • As illustrated in Figure 7-25, the contents of the input shift register are transferred to the command processor for decoding and further action.
   • RVS output goes low, indicating the beginning of conversion.

After pulling CONVST/CS high, the host controller must monitor for a low-to-high transition on the RVS pin or wait for the t_{conv_max} time (see the Timing Requirements: Conversion CycleTiming Requirements: Conversion Cycle table) to elapse before initiating a new data transfer frame.

At the end of the data transfer frame F:

• If the SCLK counter = 32, then the device treats the frame F as an optimal data transfer frame for any read or write operation. At the end of an optimal data transfer frame, the command processor treats the 32-bit contents of the input shift register as a valid command word.
• If the SCLK counter is < 32, then the device treats the frame F as a short data transfer frame.
  • The data write operation to the device in invalid and the device treats this frame as an NOP command.
  • The output data bits transferred during a short frame on the SDO-x pins are still valid data. The host controller can use the short data transfer frame to read only the required number of MSB bits from the 32-bit output shift register.
• If the SCLK counter is > 32, then the device treats the frame F as a long data transfer frame. At the end of a long data transfer frame, the command processor treats the 32-bit contents of the input shift register as a valid command word. There is no restriction on the maximum number of clocks that can be provided within any data transfer frame F. However, when the host controller provides a long data transfer frame, the last 32 bits shifted into the device prior to the CONVST/CS rising edge must constitute the desired command.