JAJSCU6B december 2016 – march 2021 ADS8661 , ADS8665
PRODUCTION DATA
The device provides an option to increase the SDO-x bus width from one bit (default, single SDO-x) to two bits (dual SDO-x) when operating with any of the SRC protocols. In order to operate the device in dual SDO mode, the SDO1_CONFIG[1:0] bits in the SDO_CTL_REG register must be set to 11b. In this mode, the ALARM/SDO-1/GPO pin functions as SDO-1.
For any particular SRC protocol, the device follows the same timing specifications for single and dual SDO modes. The only difference is that the device requires half as many clock cycles to output the same number of bits when in single SDO mode, thus reducing the minimum required clock frequency for a certain sampling rate of the ADC.