The device features an active-low RST pin that is an asynchronous digital input. In order to enter a RESET state, the RST pin must be pulled low and kept low for the t_{wl_RST} duration (as specified in the Timing Requirements: Asynchronous ResetTiming Requirements: Asynchronous ResetTiming Requirements: Asynchronous Reset table).

The device features two different types of reset functions: an application reset or a power-on reset (POR). The functionality of the RST pin is determined by the state of the RSTn_APP bit in the RST_PWRCTL_REG register.

• In order to configure the RST pin to issue an application reset, the RSTn_APP bit in the RST_PWRCTL_REG register must be configured to 1b. In this RESET state, all configuration registers (see the Register MapsRegister Maps section) are reset to their default values, the RVS pins remain low, and the SDO-x pins are tri-stated.
• The default configuration for the RST pin is to issue a power-on reset when pulled to a low level. The RSTn_APP bit is set to 0b in this state. When a POR is issued, all internal circuitry of the device (including the PGA, ADC driver, and voltage reference) are reset. When the device comes out of the POR state, the t_{D_RST_POR} time duration must be allowed for (see the Timing Requirements: Asynchronous Reset table) in order for the internal circuitry to accurately settle.

In order to exit any of the RESET states, the RST pin must be pulled high with CONVST/CS and SCLK held low. After a delay of t_{D_RST_POR} or t_{D_RST_APP} (see the Timing Requirements: Asynchronous Reset table), the device enters ACQ state and the RVS pin goes high.

To operate the device in any of the other two states (ACQ or CONV), the RST pin must be held high. With the RST pin held high, transitions on the CONVST/CS pin determine the functional state of the device. A typical conversion cycle is illustrated in Figure 6-1.