The device offers a programmable gain amplifier (PGA) at each individual analog input channel that converts the input single-ended signal into a fully differential signal to drive the internal 16-bit ADC. The PGA also adjusts the common-mode level of the input signal before being fed into the ADC to provide the maximum usage of the ADC input dynamic range.

The logic levels on the range select pins, HW_RNGSEL[1:0], determine the analog input range of all analog input channels (see the Section 7.4.1.4 section). If both range select pins are tied to a logic low, the analog input range is determined in software mode through the input range registers (see the Section 7.6 section for details). In software mode, an individual analog input range can be configured per channel. The device also supports a 20% overrange feature on all input channels in software mode. Program the D[7:0] bits from the 0x08H and 0x0AH registers to individually enable the overrange feature for channels AIN_xA. Program the same value in both registers. Program the D[7:0] bits from the 0x09H and 0x0Bh registers to individually enable the overrange feature for channels AIN_xB. Program the same value in both registers. See the 0x0AH and 0x0BH register details for the programmed register values. The programmed range of the selected channel is increased by 20%. For example, if channel AIN_0A is programmed for a ±10-V range with the overrange feature, the resultant input range is ±12 V.

In hardware mode, the range selected by the HW_RNGSEL[1:0] pins is applicable for all channels. A logic change on the HW_RNGSEL[1:0] pins has an immediate effect on the analog input range; however, there is typically a settling time of approximately 120 µs in addition to the normal acquisition time requirement for the low-pass filter option 2.

Table 7-1 lists the various gain settings achievable with the HW_RNGSEL[1:0] pin settings.