JAJSGY4B May   2013  – February 2019 ADS8862

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ADC 電源用に別個の LDO が不要
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements: 3-Wire Operation
    7. 8.7 Timing Requirements: 4-Wire Operation
    8. 8.8 Timing Requirements: Daisy-Chain
    9. 8.9 Typical Characteristics
  9. 9 Parameter Measurement Information
    1. 9.1 Equivalent Circuits
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Analog Input
      2. 10.3.2 Reference
      3. 10.3.3 Clock
      4. 10.3.4 ADC Transfer Function
    4. 10.4 Device Functional Modes
      1. 10.4.1 CS Mode
        1. 10.4.1.1 3-Wire CS Mode Without a Busy Indicator
        2. 10.4.1.2 3-Wire CS Mode With a Busy Indicator
        3. 10.4.1.3 4-Wire CS Mode Without a Busy Indicator
        4. 10.4.1.4 4-Wire CS Mode With a Busy Indicator
      2. 10.4.2 Daisy-Chain Mode
        1. 10.4.2.1 Daisy-Chain Mode Without a Busy Indicator
        2. 10.4.2.2 Daisy-Chain Mode With a Busy Indicator
  11. 11Application and Implementation
    1. 11.1 Application Information
      1. 11.1.1 ADC Reference Driver
      2. 11.1.2 ADC Input Driver
        1. 11.1.2.1 Input Amplifier Selection
        2. 11.1.2.2 Charge-Kickback Filter
    2. 11.2 Typical Applications
      1. 11.2.1 DAQ Circuit for a 1.5-µs, Full-Scale Step Response
        1. 11.2.1.1 Design Requirements
        2. 11.2.1.2 Detailed Design Procedure
      2. 11.2.2 DAQ Circuit for Lowest Distortion and Noise Performance at 680 kSPS
        1. 11.2.2.1 Design Requirements
        2. 11.2.2.2 Detailed Design Procedure
      3. 11.2.3 Ultralow-Power DAQ Circuit at 10 kSPS
        1. 11.2.3.1 Design Requirements
        2. 11.2.3.2 Detailed Design Procedure
  12. 12Power Supply Recommendations
    1. 12.1 Power-Supply Decoupling
    2. 12.2 Power Saving
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 ドキュメントのサポート
      1. 14.1.1 関連資料
    2. 14.2 ドキュメントの更新通知を受け取る方法
    3. 14.3 コミュニティ・リソース
    4. 14.4 商標
    5. 14.5 静電気放電に関する注意事項
    6. 14.6 Glossary
  15. 15メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.9 Typical Characteristics

at TA = 25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 680 kSPS (unless otherwise noted)
ADS8862 C001_SBAS572.png
Figure 4. Typical INL (VREF = 2.5 V)
ADS8862 C003_SBAS572.png
Figure 6. Typical INL (VREF = 5 V)
ADS8862 C005_SBAS572.png
Figure 8. INL vs Temperature
ADS8862 C007_SBAS572.png
Figure 10. INL vs Reference Voltage
ADS8862 C009_SBAS572.png
Figure 12. DC Input Histogram (VREF = 2.5 V)
ADS8862 C001_SBAS570.png
Figure 14. Typical FFT (VREF = 2.5 V)
ADS8862 C013_SBAS572.png
Figure 16. SNR vs Reference Voltage
ADS8862 C015_SBAS572.png
Figure 18. ENOB vs Reference Voltage
ADS8862 C017_SBAS572.png
Figure 20. SFDR vs Reference Voltage
ADS8862 C019_SBAS572.png
Figure 22. SINAD vs Temperature
ADS8862 C021_SBAS572.png
Figure 24. THD vs Temperature
ADS8862 C023_SBAS572.png
Figure 26. SNR vs Input Frequency
ADS8862 C025_SBAS572.png
Figure 28. ENOB vs Input Frequency
ADS8862 C027_SBAS572.png
Figure 30. SFDR vs Input Frequency
ADS8862 C006_SBAS570.png
Figure 32. Power Consumption vs Temperature
ADS8862 C004_SBAS570.png
Figure 34. Power Consumption vs Throughput
ADS8862 C033_SBAS572.png
Figure 36. Offset vs Temperature
ADS8862 C007_SBAS569.png
Figure 38. Typical Distribution of Gain Error
ADS8862 C009_SBAS569.png
Figure 40. Typical Distribution of Differential Nonlinearity (Minimum and Maximum)
ADS8862 C002_SBAS572.png
Figure 5. Typical DNL (VREF = 2.5 V)
ADS8862 C004_SBAS572.png
Figure 7. Typical DNL (VREF = 5 V)
ADS8862 C006_SBAS572.png
Figure 9. DNL vs Temperature
ADS8862 C008_SBAS572.png
Figure 11. DNL vs Reference Voltage
ADS8862 C010_SBAS572.png
Figure 13. DC Input Histogram (VREF = 5 V)
ADS8862 C002_SBAS570.png
Figure 15. Typical FFT (VREF = 5 V)
ADS8862 C014_SBAS572.png
Figure 17. SINAD vs Reference Voltage
ADS8862 C016_SBAS572.png
Figure 19. THD vs Reference Voltage
ADS8862 C018_SBAS572.png
Figure 21. SNR vs Temperature
ADS8862 C020_SBAS572.png
Figure 23. ENOB vs Temperature
ADS8862 C022_SBAS572.png
Figure 25. SFDR vs Temperature
ADS8862 C024_SBAS572.png
Figure 27. SINAD vs Input Frequency
ADS8862 C026_SBAS572.png
Figure 29. THD vs Input Frequency
ADS8862 C005_SBAS570.png
Figure 31. Supply Current vs Temperature
ADS8862 C003_SBAS570.png
Figure 33. Supply Current vs Throughput
ADS8862 C032_SBAS547.png
Figure 35. Power-Down Current vs Temperature
ADS8862 C034_SBAS572.png
Figure 37. Gain Error vs Temperature
ADS8862 C008_SBAS569.png
Figure 39. Typical Distribution of Offset Error
ADS8862 C010_SBAS569.png
Figure 41. Typical Distribution of Integral
Nonlinearity (Minimum and Maximum)