11.1.2.1 Input Amplifier Selection

Selection criteria for the input amplifiers is highly dependent on the input signal type as well as the performance goals of the data acquisition system. Some key amplifier specifications to consider while selecting an appropriate amplifier to drive the inputs of the ADC are:

• Small-signal bandwidth. Select the small-signal bandwidth of the input amplifiers to be as high as possible after meeting the power budget of the system. Higher bandwidth reduces the closed-loop output impedance of the amplifier, thus allowing the amplifier to more easily drive the low cutoff frequency RC filter (see the Antialiasing Filter section) at the inputs of the ADC. Higher bandwidth also minimizes the harmonic distortion at higher input frequencies. In order to maintain the overall stability of the input driver circuit, select the amplifier bandwidth as described in Equation 2:
Equation 2.
• Noise. Noise contribution of the front-end amplifiers must be as low as possible to prevent any degradation in SNR performance of the system. As a rule of thumb, to ensure that the noise performance of the data acquisition system is not limited by the front-end circuit, the total noise contribution from the front-end circuit must be kept below 20% of the input-referred noise of the ADC. Noise from the input driver circuit is band-limited by designing a low cutoff frequency RC filter, as explained in Equation 3.
Equation 3.
where
• V_{1 / f_AMP_PP} is the peak-to-peak flicker noise in µV,
• e_{n_RMS} is the amplifier broadband noise density in nV/√Hz,
• f_–3dB is the 3-dB bandwidth of the RC filter, and
• N_G is the noise gain of the front-end circuit, which is equal to 1 in a buffer configuration.
• Distortion. Both the ADC and the input driver introduce nonlinearity in a data acquisition block. As a rule of thumb, to ensure that the distortion performance of the data acquisition system is not limited by the front-end circuit, the distortion of the input driver must be at least 10 dB lower than the distortion of the ADC, as shown in Equation 4.
Equation 4.
• Settling Time. For dc signals with fast transients that are common in a multiplexed application, the input signal must settle within an 18-bit accuracy at the device inputs during the acquisition time window. This condition is critical to maintain the overall linearity performance of the ADC. Typically, the amplifier data sheets specify the output settling performance only up to 0.1% to 0.001%, which may not be sufficient for the desired 18-bit accuracy. Therefore, always verify the settling behavior of the input driver by TINA™-SPICE simulations before selecting the amplifier.

11.1.2.2 Antialiasing Filter

Converting analog-to-digital signals requires sampling an input signal at a constant rate. Any higher frequency content in the input signal beyond half the sampling frequency is digitized and folded back into the low-frequency spectrum. This process is called aliasing. Therefore, an analog, antialiasing filter must be used to remove the harmonic content from the input signal before being sampled by the ADC. An antialiasing filter is designed as a low-pass, RC filter, for which the 3-dB bandwidth is optimized based on specific application requirements. For dc signals with fast transients (including multiplexed input signals), a high-bandwidth filter is designed to allow accurately settling the signal at the inputs of the ADC during the small acquisition time window. For ac signals, keep the filter bandwidth low to band-limit the noise fed into the input of the ADC, thereby increasing the signal-to-noise ratio (SNR) of the system.

Besides filtering the noise from the front-end drive circuitry, the RC filter also helps attenuate the sampling charge injection from the switched-capacitor input stage of the ADC. A differential filter capacitor, C_FLT, is connected across the inputs of the ADC (as shown in Figure 64). This capacitor helps reduce the sampling charge injection and provides a charge bucket to quickly charge the internal sample-and-hold capacitors during the acquisition process. As a rule of thumb, the value of this capacitor must be at least 10 times the specified value of the ADC sampling capacitance. For the ADS8881, the input sampling capacitance is equal to 59 pF, thus the value of C_FLT must be greater than 590 pF. The capacitor must be a COG- or NPO-type because these capacitor types have a high-Q, low-temperature coefficient, and stable electrical characteristics under varying voltages, frequency, and time.

Figure 64. Antialiasing Filter

Note that driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier marginally unstable. To avoid amplifier stability issues, series isolation resistors (R_FLT) are used at the output of the amplifiers. A higher value of R_FLT is helpful from the amplifier stability perspective, but adds distortion as a result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance, input signal frequency, and input signal amplitude. Therefore, the selection of R_FLT requires balancing the stability and distortion of the design. For the ADS8881, TI recommends limiting the value of R_FLT to a maximum of 22 Ω in order to avoid any significant degradation in linearity performance. The tolerance of the selected resistors can be chosen as 1% because the use of a differential capacitor at the input balances the effects resulting from any resistor mismatch.

The input amplifier bandwidth must be much higher than the cutoff frequency of the antialiasing filter. TI strongly recommends performing a SPICE simulation to confirm that the amplifier has more than 40° phase margin with the selected filter. Simulation is critical because even with high-bandwidth amplifiers, some amplifiers might require more bandwidth than others to drive similar filters. If an amplifier has less than a 40° phase margin with 22-Ω resistors, using a different amplifier with higher bandwidth or reducing the filter cutoff frequency with a larger differential capacitor is advisable.

11.2.1.1 Design Requirements

Step input signals are common in multiplexed applications when switching between different channels. In a worst-case scenario, one channel is at the negative full-scale (NFS) and the other channel is at the positive full-scale (PFS) voltage, in which case the step size is the full-scale range (FSR) of the ADC when the MUX channel is switched.

Design an application circuit optimized for using the ADS8881 to achieve

• full-scale step input settling to 18-bit accuracy and
• INL of < ±2 LSB and
• maximum specified throughput of 1 MSPS

11.2.1.2 Detailed Design Procedure

The application circuit is shown in Figure 65.

In such applications, the primary design requirement is to ensure that the full-scale step input signal settles to 18-bit accuracy at the ADC inputs. This condition is critical to achieve the excellent linearity specifications of the ADC. Therefore, the bandwidth of the antialiasing RC filter must be large enough to allow optimal settling of the input signal during the ADC acquisition time. The filter capacitor helps reduce the sampling charge injection at the ADC inputs, but degrades the phase margin of the driving amplifier, thereby leading to stability issues. Amplifier stability is maintained by the series isolation resistor.

The application circuit in Figure 65 shows the schematic of a complete reference driver circuit that generates a voltage of 4.5 V dc using a single 5-V supply. This circuit is suitable to drive the reference of the ADS8881 at higher sampling rates up to 1 MSPS. The reference voltage of 4.5 V in this design is generated by the high-precision, low-noise REF5045 circuit. The output broadband noise of the reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of 160 Hz.

The reference buffer is designed with the THS4281 and OPA333 in a composite architecture to achieve superior dc and ac performance at a reduced power consumption, compared to using a single high-performance amplifier. The THS4281 is a high-bandwidth amplifier with a very low output impedance of 1 Ω at a frequency of 1 MHz. The low output impedance makes the THS4281 a good choice for driving a high capacitive load to regulate the voltage at the reference input of the ADC. The high offset and drift specifications of the THS4281 are corrected by using a dc-correcting amplifier (OPA333) inside the feedback loop. The composite scheme inherits the extremely low offset and temperature drift specifications of the OPA333.

For the input driving amplifiers, key specifications include rail-to-rail input and output swing, high bandwidth, high slew rate, and fast settling time. The OPA350 CMOS amplifier meets all these specification requirements for this circuit with a single-supply and low quiescent current. The component values of the antialiasing filter are selected to meet the settling requirements of the system as well as to maintain the stability of the input driving amplifiers.

11.2.1.3 Application Curve

18-bit INL

Figure 66. Limited Point Linearity

For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, see 18-Bit Data Acquisition (DAQ) Block Optimized for 1-μs Full-Scale Step Response (TIDU012).

11.2.2.1 Design Requirements

Design an application circuit optimized for using the ADS8881 to achieve

• ENOB > 17 bits and
• < 35 mW of total power consumption and
• maximum specified throughput of 1 MSPS

11.2.2.2 Detailed Design Procedure

The application circuit in Figure 67 shows the schematic of a complete reference driver circuit that generates a voltage of 4.5 V dc using a single 5-V supply. This circuit is suitable to drive the reference of the ADS8881 at higher sampling rates up to 1 MSPS. The reference voltage of 4.5 V in this design is generated by the high-precision, low-noise REF5045 circuit. The output broadband noise of the reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of 160 Hz.

The reference buffer is designed with the THS4281 and OPA333 in a composite architecture to achieve superior dc and ac performance at a reduced power consumption, compared to using a single high-performance amplifier. The THS4281 is a high-bandwidth amplifier with a very low output impedance of 1 Ω at a frequency of 1 MHz. The low output impedance makes the THS4281 a good choice for driving a high capacitive load to regulate the voltage at the reference input of the ADC. The high offset and drift specifications of the THS4281 are corrected by using a dc-correcting amplifier (OPA333) inside the feedback loop. The composite scheme inherits the extremely low offset and temperature drift specifications of the OPA333.

In such applications, the input driver must be low in power and noise as well as able to support rail-to-rail input and output swing with a single supply. A high amplifier bandwidth is also preferred to help attenuate high-frequency distortion. However, oftentimes bandwidth and noise are traded off with the power consumption of the amplifier. This circuit uses the OPA320 as the front-end driving amplifier because this device has a relatively low noise density of 7 nV/√Hz for a maximum-specified quiescent current of 1.45 mA per channel.

The noise contribution from the front-end amplifier is band-limited by the 3-dB bandwidth of the RC filter and is designed to be 1.65 MHz in this application. Again, the component values of the antialiasing filter are carefully selected to maintain the stability of the input driving amplifiers.

11.2.2.3 Application Curve

Vdiff close to 0 V, 32768 data points, standard deviation = 0.82 bits, ENOB (dc) = 17.18 bits

Figure 68. DC Input Histogram

For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, see 18-Bit, 1-MSPS Data Acquisition (DAQ) Block Optimized for Lowest Power (SLAU513).

11.2.3.1 Design Requirements

Design an application circuit optimized for using the ADS8881 to achieve

• > 98.5-dB SNR, < –110-dB THD and
• ± 1.5-LSB linearity and
• maximum specified throughput of 1 MSPS

11.2.3.2 Detailed Design Procedure

The application circuits are shown in Figure 69 and Figure 70. In both applications, the input signal is processed through a high-bandwidth, low-distortion, fully-differential amplifier (FDA) designed in an inverting gain configuration and a low-pass RC filter before being fed into the ADC.

The reference driver circuit, shown in Figure 69 and Figure 70, generates a voltage of 4.5 V dc using a single 5-V supply. This circuit is suitable to drive the reference of the ADS8881 at higher sampling rates up to 1 MSPS. The reference voltage of 4.5 V in this design is generated by the high-precision, low-noise REF5045 circuit. The output broadband noise of the reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of 160 Hz.

The reference buffer is designed with the THS4281 and OPA333 in a composite architecture to achieve superior dc and ac performance at a reduced power consumption, compared to using a single high-performance amplifier. The THS4281 is a high-bandwidth amplifier with a very low output impedance of 1 Ω at a frequency of 1 MHz. The low output impedance makes the THS4281 a good choice for driving a high capacitive load to regulate the voltage at the reference input of the ADC. The high offset and drift specifications of the THS4281 are corrected by using a dc-correcting amplifier (OPA333) inside the feedback loop. The composite scheme inherits the extremely low offset and temperature drift specifications of the OPA333.

As a rule of thumb, the distortion from the input driver must be at least 10 dB less than the ADC distortion. The distortion resulting from variation in the common-mode signal is eliminated by using the FDA in an inverting gain configuration that establishes a fixed common-mode level for the circuit. This configuration also eliminates the requirement of a rail-to-rail swing at the amplifier input. Therefore, these circuits use the low-power THS4521 as an input driver that provides exceptional ac performance because of its extremely low-distortion and high-bandwidth specifications.

In addition, the components of the antialiasing filter are such that the noise from the front-end circuit is kept low without adding distortion to the input signal.

The circuit in Figure 69 shows a fully-differential DAQ block optimized for low distortion and noise using the THS4521 and ADS8881. This front-end circuit configuration requires a differential signal at the input of the FDA and provides a differential output to drive the ADC inputs. The common-mode voltage of the input signal provided to the ADC is set by the V_OCM pin of the THS4521 (not shown in Figure 69). To use the complete dynamic range of the ADC, V_OCM can be set to V_REF / 2 by using a simple resistive divider. However, note that the ADS8881 allows the common-mode input voltage (V_CM) to be set to any value in the range of 0 V to V_REF.

The circuit in Figure 70 shows a single-ended to differential DAQ block optimized for low distortion and noise using the THS4521 and the ADS8881. This front-end circuit configuration requires a single-ended ac signal at the input of the FDA and provides a fully-differential output to drive the ADC inputs. The common-mode voltage of the input signal provided to the ADC is set by the V_OCM pin of the THS4521 (not shown in Figure 70). To use the complete dynamic range of the ADC, V_OCM can be set to V_REF / 2 by using a simple resistive divider. However, note that the ADS8881 allows the common-mode input voltage (V_CM) to be set to any value in the range of 0 V to V_REF.

11.2.3.3 Application Curve

fIN = 10 kHz, SNR = 99 dB, THD = –112 dB

Figure 71. FFT Plot

For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, see 18-Bit, 1-MSPS Data Acquisition (DAQ) Block Optimized for Lowest Distortion and Noise (SLAU515).

11.2.4.1 Design Requirements

Portable and battery-powered applications require ultralow-power consumption and do not need very high throughput from the ADC.

Design a single-supply, data acquisition circuit optimized for using the ADS8881 to achieve

• ENOB > 16 bits and
• Ultralow-power consumption of < 1 mW at throughput of 10 kSPS.

11.2.4.2 Detailed Design Procedure

The application circuit in Figure 72 shows the schematic of a complete reference driver circuit that generates a voltage of 2.5 V dc using a single 3.3-V supply. This ultralow power reference block is suitable to drive the ADS8881 for power-sensitive applications at a relatively lower throughput. This design uses the high-precision REF3325 circuit that provides an accurate 2.5-V reference voltage at an extremely low quiescent current of 5 µA. The output broadband noise of the reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of 16 Hz.

The reference buffer is designed with the low-power OPA313 that can operate from a 3.3-V supply at an extremely low quiescent current of 50 µA. The wideband noise contribution from the amplifier is limited by a lowpass filter of a cutoff frequency equal to 1.5 kHz, formed by a 4.7-Ω resistor in combination with a 22-μF capacitor. The 4.7-Ω series resistor creates an additional drop in the reference voltage that is corrected by a dual-feedback configuration.

The input driver circuit uses extremely low-power, dual amplifiers (such as the OPA2333) with a maximum quiescent current of 28 µA per channel to drive the ADC inputs. The input amplifiers are configured in a modified unity-gain buffer configuration. The filter capacitor at the ADC inputs attenuates the sampling charge-injection noise from the ADC but effects the stability of the input amplifiers by degrading the phase margin. This attenuation requires a series isolation resistor to maintain amplifier stability. The value of the series resistor is directly proportional to the open-loop output impedance of the driving amplifier to maintain stability, which is high (in the order of kΩ) in the case of low-power amplifiers such as the OPA333. Therefore, a high value of 1 kΩ is selected for the series resistor at the ADC inputs. However, this series resistor creates an additional voltage drop in the signal path, thereby leading to linearity and distortion issues. The dual-feedback configuration used in Figure 72 corrects for this additional voltage drop and maintains system performance at ultralow-power consumption.

11.2.4.3 Application Curve

Vdiff close to 0 V, 32768 data points, standard deviation = 1.7 bits, ENOB (dc) = 16.3 bits

Figure 73. DC Input Histogram

For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, see 18-Bit, 10kSPS Data Acquisition (DAQ) Block Optimized for Ultra Low Power < 1mW (SLAU514).