SBAS547D May   2013  – August 2015 ADS8881

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Companion Products
  6. 6 Device Comparison
  7. 7 Pin Configurations and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements: 3-Wire Operation
    7. 8.7 Timing Requirements: 4-Wire Operation
    8. 8.8 Timing Requirements: Daisy-Chain
    9. 8.9 Typical Characteristics
  9. 9 Parametric Measurement Information
    1. 9.1 Equivalent Circuits
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Analog Input
      2. 10.3.2 Reference
      3. 10.3.3 Clock
      4. 10.3.4 ADC Transfer Function
    4. 10.4 Device Functional Modes
      1. 10.4.1 CS Mode
        1. 10.4.1.1 3-Wire CS Mode Without a Busy Indicator
        2. 10.4.1.2 3-Wire CS Mode With a Busy Indicator
        3. 10.4.1.3 4-Wire CS Mode Without a Busy Indicator
        4. 10.4.1.4 4-Wire CS Mode With a Busy Indicator
      2. 10.4.2 Daisy-Chain Mode
        1. 10.4.2.1 Daisy-Chain Mode Without a Busy Indicator
        2. 10.4.2.2 Daisy-Chain Mode With a Busy Indicator
  11. 11Application and Implementation
    1. 11.1 Application Information
      1. 11.1.1 ADC Reference Driver
      2. 11.1.2 ADC Input Driver
        1. 11.1.2.1 Input Amplifier Selection
        2. 11.1.2.2 Antialiasing Filter
    2. 11.2 Typical Applications
      1. 11.2.1 DAQ Circuit for a 1-µs, Full-Scale Step Response
        1. 11.2.1.1 Design Requirements
        2. 11.2.1.2 Detailed Design Procedure
        3. 11.2.1.3 Application Curve
      2. 11.2.2 Low-Power DAQ Circuit for Excellent Dynamic Performance at 1 MSPS
        1. 11.2.2.1 Design Requirements
        2. 11.2.2.2 Detailed Design Procedure
        3. 11.2.2.3 Application Curve
      3. 11.2.3 DAQ Circuit for Lowest Distortion and Noise Performance at 1 MSPS
        1. 11.2.3.1 Design Requirements
        2. 11.2.3.2 Detailed Design Procedure
        3. 11.2.3.3 Application Curve
      4. 11.2.4 Ultralow-Power DAQ Circuit at 10 kSPS
        1. 11.2.4.1 Design Requirements
        2. 11.2.4.2 Detailed Design Procedure
        3. 11.2.4.3 Application Curve
  12. 12Power-Supply Recommendations
    1. 12.1 Power-Supply Decoupling
    2. 12.2 Power Saving
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Device Support
      1. 14.1.1 Development Support
    2. 14.2 Documentation Support
      1. 14.2.1 Related Documentation
    3. 14.3 Receiving Notification of Documentation Updates
    4. 14.4 Community Resources
    5. 14.5 Trademarks
    6. 14.6 Electrostatic Discharge Caution
    7. 14.7 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
AINP to GND or AINN to GND –0.3 REF + 0.3 V
AVDD to GND or DVDD to GND –0.3 4 V
REF to GND –0.3 5.7 V
Digital input voltage to GND –0.3 DVDD + 0.3 V
Digital output to GND –0.3 DVDD + 0.3 V
Operating temperature, TA ADS8881C 0 70 °C
ADS8881I –40 85
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

8.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
AVDD Analog power supply 3 V
DVDD Digital power supply 3 V
VREF Reference voltage 5 V

8.4 Thermal Information

THERMAL METRIC ADS8881 UNIT
DGS (VSSOP) DRC (VSON)
10 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance 151.9 111.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 45.4 46.4 °C/W
RθJB Junction-to-board thermal resistance 72.2 45.9 °C/W
ψJT Junction-to-top characterization parameter 3.3 3.5 °C/W
ψJB Junction-to-board characterization parameter 70.9 45.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W

8.5 Electrical Characteristics

All minimum and maximum specifications are at AVDD = 3 V, DVDD = 3 V, VREF = 5 V, VCM = VREF / 2 V,
and fSAMPLE = 1 MSPS, over the operating free-air temperature range, unless otherwise noted.
Typical specifications are at TA = 25°C, AVDD = 3 V, and DVDD = 3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Full-scale input span(1)(8) AINP – AINN –VREF VREF V
Operating input range(1)(8) AINP –0.1 VREF + 0.1 V
AINN –0.1 VREF + 0.1
VCM Input common-mode range 0 VREF / 2 VREF V
CI Input capacitance AINP and AINN terminal to GND 59 pF
EXTERNAL REFERENCE INPUT
VREF Input range ADS8881C 3 5 V
ADS8881I 2.5 5
Reference input current During conversion, 1-MHz sample rate, mid-code 300 μA
Reference leakage current 250 nA
CREF Decoupling capacitor at the REF input 10 22 µF
Input leakage current During acquisition for dc input 5 nA
SYSTEM PERFORMANCE
Resolution 18 Bits
NMC No missing codes 18 Bits
DNL Differential linearity ADS8881C –0.99 ±0.6 1 LSB(2)
ADS8881I –0.99 ±0.7 1.5
INL Integral linearity(5) ADS8881C –2 ±1.2 2 LSB(2)
ADS8881I –3 ±1.5 3
EO Offset error(3) –4 ±1 4 mV
Offset error drift with temperature ±1.5 µV/°C
EG Gain error –0.01 ±0.005 0.01 %FSR
Gain error drift with temperature ±0.15 ppm/°C
CMRR Common-mode rejection ratio 90 100 dB
PSRR Power-supply rejection ratio At mid-code 80 dB
Transition noise 0.7 LSB
SAMPLING DYNAMICS
tconv Conversion time 500 710 ns
tACQ Acquisition time 290 ns
Maximum throughput rate
with or without latency		 1000 kHz
Aperture delay 4 ns
Aperture jitter, RMS 5 ps
Step response Settling to 18-bit accuracy 290 ns
Overvoltage recovery Settling to 18-bit accuracy 290 ns
DYNAMIC CHARACTERISTICS
SINAD Signal-to-noise + distortion(7) At 1 kHz, VREF = 5 V 98 99.9 dB
At 10 kHz, VREF = 5 V 98.7
At 100 kHz, VREF = 5 V 93.3
SNR Signal-to-noise ratio(7) At 1 kHz, VREF = 5 V 98.5 100 dB
At 10 kHz, VREF = 5 V 99.5
At 100 kHz, VREF = 5 V 93.5
THD Total harmonic distortion(7)(4) At 1 kHz, VREF = 5 V –115 dB
At 10 kHz, VREF = 5 V –112
At 100 kHz, VREF = 5 V –102
SFDR Spurious-free dynamic range(7) At 1 kHz, VREF = 5 V 115 dB
At 10 kHz, VREF = 5 V 112
At 100 kHz, VREF = 5 V 102
BW–3dB –3-dB small-signal bandwidth 30 MHz
POWER-SUPPLY REQUIREMENTS
Power-supply voltage AVDD Analog supply 2.7 3 3.6 V
DVDD Digital supply range for SCLK > 40 MHz 2.7 3 3.6
Digital supply range for SCLK < 40 MHz 1.65 1.8 3.6
Supply current AVDD 1-MHz sample rate, AVDD = 3 V 1.8 2.4 mA
PVA Power dissipation 1-MHz sample rate, AVDD = 3 V 5.5 7.2 mW
100-kHz sample rate, AVDD = 3 V 0.55
10-kHz sample rate, AVDD = 3 V 55 μW
IAPD Device power-down current(6) 50 nA
DIGITAL INPUTS: LOGIC FAMILY (CMOS)
VIH High-level input voltage 1.65 V < DVDD < 2.3 V 0.8 × DVDD DVDD + 0.3 V
2.3 V < DVDD < 3.6 V 0.7 × DVDD DVDD + 0.3
VIL Low-level input voltage 1.65 V < DVDD < 2.3 V –0.3 0.2 × DVDD V
2.3 V < DVDD < 3.6 V –0.3 0.3 × DVDD
ILK Digital input leakage current ±10 ±100 nA
DIGITAL OUTPUTS: LOGIC FAMILY (CMOS)
VOH High-level output voltage IO = 500-μA source, CLOAD = 20 pF 0.8 × DVDD DVDD V
VOL Low-level output voltage IO = 500-μA sink, CLOAD = 20 pF 0 0.2 × DVDD V
TEMPERATURE RANGE
TA Operating free-air temperature ADS8881C 0 70 °C
ADS8881I –40 85
(1) Ideal input span, does not include gain or offset error.
(2) LSB = least significant bit. 1 LSB at 18-bits is approximately 3.8 ppm.
(3) Measured relative to actual measured reference.
(4) Calculated on the first nine harmonics of the input frequency.
(5) This parameter is the endpoint INL, not best-fit.
(6) The device automatically enters a power-down state at the end of every conversion, and remains in power-down during the acquisition phase.
(7) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-scale, unless otherwise specified.
(8) Specified for VCM = VREF / 2; see the Analog Input section for the effect of VCM on the full-scale input range.

8.6 Timing Requirements: 3-Wire Operation

All specifications are at AVDD = 3 V, DVDD = 3 V, and over the operating free-air temperature range, unless otherwise noted.
MIN TYP MAX UNIT
tACQ Acquisition time 290 ns
tconv Conversion time TA in the range –40°C to 85°C 500 710 ns
TA in the range 0°C to 70°C 500 700
tconv Conversion time 500 ns
1/fsample Time between conversions 1000 ns
twh-CNV Pulse duration: CONVST high 10 ns
fSCLK SCLK frequency 70 MHz
tSCLK SCLK period 14.3 ns
tclkl SCLK low time 0.45 0.55 tSCLK
tclkh SCLK high time 0.45 0.55 tSCLK
th-CK-DO SCLK falling edge to current data invalid 3 ns
td-CK-DO SCLK falling edge to next data valid delay TA in the range –40°C to 85°C 13.4 ns
TA in the range 0°C to 70°C 11.7
TA in the range 25°C to 50°C 10.7
td-CNV-DO Enable time: CONVST low to MSB valid 12.3 ns
td-CNV-DOhz Disable time: CONVST high or last SCLK falling edge to DOUT 3-state (CS mode) 13.2 ns
tquiet Quiet time TA in the range –40°C to 85°C 20 ns
TA in the range 0°C to 70°C 13
ADS8881 tim_3wire_op_bas547.gif Figure 1. 3-Wire Operation: CONVST Functions as Chip Select

NOTE: Figure 1 shows the timing diagram for the 3-Wire CS Mode Without a Busy Indicator interface option. However, the timing parameters specified in Timing Requirements: 3-Wire Operation are also applicable for the 3-Wire CS Mode With a Busy Indicator interface option, unless otherwise specified; see the Device Functional Modes section for specific details for each interface option.

8.7 Timing Requirements: 4-Wire Operation

All specifications are at AVDD = 3 V, DVDD = 3 V, and over the operating free-air temperature range, unless otherwise noted.
MIN TYP MAX UNIT
tACQ Acquisition time 290 ns
tconv Conversion time TA in the range –40°C to 85°C 500 710 ns
TA in the range 0°C to 70°C 500 700
tconv Conversion time 500 ns
1/fsample Time between conversions 1000 ns
twh-DI Pulse duration: DIN high 10 ns
twl-CNV Pulse width: CONVST low 20 ns
td-DI-DO Delay time: DIN low to MSB valid 12.3 ns
td-DI-DOhz Delay time: DIN high or last SCLK falling edge to DOUT 3-state 13.2 ns
tsu-DI-CNV Setup time: DIN high to CONVST rising edge 7.5 ns
th-DI-CNV Hold time: DIN high from CONVST rising edge (see Figure 63) 0 ns
ADS8881 tim_4wire_op_bas547.gif Figure 2. 4-Wire Operation: DIN Functions as Chip Select

NOTE: Figure 2 shows the timing diagram for the 4-Wire CS Mode Without a Busy Indicator interface option. However, the timing parameters specified in Timing Requirements: 4-Wire Operation are also applicable for the 4-Wire CS Mode With a Busy Indicator interface option, unless otherwise specified; see the Device Functional Modes section for specific details for each interface option.

8.8 Timing Requirements: Daisy-Chain

All specifications are at AVDD = 3 V, DVDD = 3 V, and over the operating free-air temperature range, unless otherwise noted.
MIN TYP MAX UNIT
tACQ Acquisition time 290 ns
tconv Conversion time TA in the range -40°C to 85°C 500 710 ns
TA in the range 0°C to 70°C 500 700
tconv Conversion time 500 ns
1/fsample Time between conversions 1000 ns
tsu-CK-CNV Setup time: SCLK valid to CONVST rising edge 5 ns
th-CK-CNV Hold time: SCLK valid from CONVST rising edge 5 ns
tsu-DI-CNV Setup time: DIN low to CONVST rising edge (see Figure 2) 7.5 ns
th-DI-CNV Hold time: DIN low from CONVST rising edge (see Figure 63) 0 ns
tsu-DI-CK Setup time: DIN valid to SCLK falling edge 1.5 ns
ADS8881 tim_daisy_op_bas547.gif Figure 3. Daisy-Chain Operation: Two Devices

NOTE: Figure 3 shows the timing diagram for the Daisy-Chain Mode Without a Busy Indicator interface option. However, the timing parameters specified in Timing Requirements: Daisy-Chain are also applicable for the Daisy-Chain Mode With a Busy Indicator interface option, unless otherwise specified; see the Device Functional Modes section for specific details for each interface option.

8.9 Typical Characteristics

At TA = 25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 1 MSPS, unless otherwise noted.
ADS8881 C001_SBAS547.png
Figure 4. Typical INL (VREF = 2.5 V)
ADS8881 C003_SBAS547.png
Figure 6. Typical INL (VREF = 5 V)
ADS8881 C005_SBAS547.png
Figure 8. INL vs Temperature
ADS8881 C007_SBAS547.png
Figure 10. INL vs Reference Voltage
ADS8881 C009_SBAS547.png
Figure 12. DC Input Histogram (VREF = 2.5 V)
ADS8881 C011_SBAS547.png
Figure 14. Typical FFT (VREF = 2.5 V)
ADS8881 C013_SBAS547.png
Figure 16. SNR vs Reference Voltage
ADS8881 C015_SBAS547.png
Figure 18. ENOB vs Reference Voltage
ADS8881 C017_SBAS547.png
Figure 20. SFDR vs Reference Voltage
ADS8881 C019_SBAS547.png
Figure 22. SINAD vs Temperature
ADS8881 C021_SBAS547.png
Figure 24. THD vs Temperature
ADS8881 C023_SBAS547.png
Figure 26. SNR vs Input Frequency
ADS8881 C025_SBAS547.png
Figure 28. ENOB vs Input Frequency
ADS8881 C027_SBAS547.png
Figure 30. SFDR vs Input Frequency
ADS8881 C029_SBAS547.png
Figure 32. Power Consumption vs Temperature
ADS8881 C031_SBAS547.png
Figure 34. Power Consumption vs Throughput
ADS8881 C033_SBAS547.png
Figure 36. Offset vs Temperature
ADS8881 C035_SBAS547.png
Figure 38. CMRR vs Input Frequency
ADS8881 C037_SBAS547.png
Figure 40. Typical Distribution of Offset Error
ADS8881 C039_SBAS547.png
Figure 42. Typical Distribution of Integral
Nonlinearity (Minimum and Maximum)
ADS8881 C002_SBAS547.png
Figure 5. Typical DNL (VREF = 2.5 V)
ADS8881 C004_SBAS547.png
Figure 7. Typical DNL (VREF = 5 V)
ADS8881 C006_SBAS547.png
Figure 9. DNL vs Temperature
ADS8881 C008_SBAS547.png
Figure 11. DNL vs Reference Voltage
ADS8881 C010_SBAS547.png
Figure 13. DC Input Histogram (VREF = 5 V)
ADS8881 C012_SBAS547.png
Figure 15. Typical FFT (VREF = 5 V)
ADS8881 C014_SBAS547.png
Figure 17. SINAD vs Reference Voltage
ADS8881 C016_SBAS547.png
Figure 19. THD vs Reference Voltage
ADS8881 C018_SBAS547.png
Figure 21. SNR vs Temperature
ADS8881 C020_SBAS547.png
Figure 23. ENOB vs Temperature
ADS8881 C022_SBAS547.png
Figure 25. SFDR vs Temperature
ADS8881 C024_SBAS547.png
Figure 27. SINAD vs Input Frequency
ADS8881 C026_SBAS547.png
Figure 29. THD vs Input Frequency
ADS8881 C028_SBAS547.png
Figure 31. Supply Current vs Temperature
ADS8881 C030_SBAS547.png
Figure 33. Supply Current vs Throughput
ADS8881 C032_SBAS547.png
Figure 35. Power-Down Current vs Temperature
ADS8881 C034_SBAS547.png
Figure 37. Gain Error vs Temperature
ADS8881 C036_SBAS547.png
Figure 39. Typical Distribution of Gain Error
ADS8881 C038_SBAS547.png
Figure 41. Typical Distribution of Differential Nonlinearity (Minimum and Maximum)