JAJSCA2B June   2016  – January 2018 ADS8910B , ADS8912B , ADS8914B

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ADS89xxB内蔵の機能によりシステムを簡単に設計
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 LDO Module
      2. 7.3.2 Reference Buffer Module
      3. 7.3.3 Converter Module
        1. 7.3.3.1 Sample-and-Hold Circuit
        2. 7.3.3.2 Internal Oscillator
        3. 7.3.3.3 ADC Transfer Function
      4. 7.3.4 Interface Module
    4. 7.4 Device Functional Modes
      1. 7.4.1 RST State
      2. 7.4.2 ACQ State
      3. 7.4.3 CNV State
    5. 7.5 Programming
      1. 7.5.1 Output Data Word
      2. 7.5.2 Data Transfer Frame
      3. 7.5.3 Interleaving Conversion Cycles and Data Transfer Frames
      4. 7.5.4 Data Transfer Protocols
        1. 7.5.4.1 Protocols for Configuring the Device
        2. 7.5.4.2 Protocols for Reading From the Device
          1. 7.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols
          2. 7.5.4.2.2 SPI-Compatible Protocols with Bus Width Options
          3. 7.5.4.2.3 Source-Synchronous (SRC) Protocols
            1. 7.5.4.2.3.1 Output Clock Source Options with SRC Protocols
            2. 7.5.4.2.3.2 Bus Width Options With SRC Protocols
            3. 7.5.4.2.3.3 Output Data Rate Options With SRC Protocols
      5. 7.5.5 Device Setup
        1. 7.5.5.1 Single Device: All multiSPI Options
        2. 7.5.5.2 Single Device: Minimum Pins for a Standard SPI Interface
        3. 7.5.5.3 Multiple Devices: Daisy-Chain Topology
        4. 7.5.5.4 Multiple Devices: Star Topology
    6. 7.6 Register Maps
      1. 7.6.1 Device Configuration and Register Maps
        1. 7.6.1.1 PD_CNTL Register (address = 04h) [reset = 00h]
          1. Table 11. PD_CNTL Register Field Descriptions
        2. 7.6.1.2 SDI_CNTL Register (address = 008h) [reset = 00h]
          1. Table 12. SDI_CNTL Register Field Descriptions
        3. 7.6.1.3 SDO_CNTL Register (address = 0Ch) [reset = 00h]
          1. Table 13. SDO_CNTL Register Field Descriptions
        4. 7.6.1.4 DATA_CNTL Register (address = 010h) [reset = 00h]
          1. Table 14. DATA_CNTL Register Field Descriptions
        5. 7.6.1.5 PATN_LSB Register (address = 014h) [reset = 00h]
          1. Table 15. PATN_LSB Register Field Descriptions
        6. 7.6.1.6 PATN_MID Register (address = 015h) [reset = 00h]
          1. Table 16. PATN_MID Register Field Descriptions
        7. 7.6.1.7 PATN_MSB Register (address = 016h) [reset = 00h]
          1. Table 17. PATN_MSB Register Field Descriptions
        8. 7.6.1.8 OFST_CAL Register (address = 020h) [reset = 00h]
          1. Table 18. OFST_CAL Register Field Descriptions
        9. 7.6.1.9 REF_MRG Register (address = 030h) [reset = 00h]
          1. Table 19. REF_MRG Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ADC Reference Driver
      2. 8.1.2 ADC Input Driver
        1. 8.1.2.1 Charge-Kickback Filter
        2. 8.1.2.2 Input Amplifier Selection
    2. 8.2 Typical Application
      1. 8.2.1 Data Acquisition (DAQ) Circuit for Lowest Distortion and Noise Performance With Differential Input
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DAQ Circuit With FDA Input Driver and Single-Ended or Differential Input
      3. 8.2.3 Design Requirements
      4. 8.2.4 Detailed Design Procedure
      5. 8.2.5 Application Curves
  9. 9 Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Signal Path
      2. 10.1.2 Grounding and PCB Stack-Up
      3. 10.1.3 Decoupling of Power Supplies
      4. 10.1.4 Reference Decoupling
      5. 10.1.5 Differential Input Decoupling
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 関連リンク
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

At RVDD = 5.5 V, DVDD = 1.65 V to 5.5 V, VREF = 5 V, and maximum throughput (unless otherwise noted).
Minimum and maximum values at TA = –40°C to +125°C; typical values at TA = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
FSR Full-scale input range
(AINP – AINM)		 –VREF VREF V
VIN Absolute input voltage
(AINP and AINM to REFM)		 0 VREF V
VCM Common-mode voltage
(AINP + AINM) / 2		 (VREF / 2) – 0.1 VREF / 2 (VREF / 2) + 0.1 V
CIN Input capacitance Sample mode 60 pF
Hold mode 4 pF
VOLTAGE REFERENCE INPUT (REFIN)
IREF Reference input current VREF = 5 V 0.1 1 µA
CREF Internal capacitance 10 pF
REFERENCE BUFFER OUTPUT (REFBUFOUT)
V(RO) Reference buffer offset voltage
(VREFBUFOUT – VREF)		 With EN_MARG = 0b(1), TA = 25°C(5) –250 250 µV
CREFBUF External ceramic decoupling capacitor 10 22 µF
RESR External series resistor 0 1 1.3 Ω
ISHRT Short-circuit current 30 mA
Margining range With EN_MARG = 1b(1) ±4.5 mV
Margining resolution With EN_MARG = 1b(1) 280 µV
DC ACCURACY(2) (CREFBUF = 22 µF, RESR = 1 Ω)
Resolution 18 Bits
NMC No missing codes 18 Bits
INL Integral nonlinearity(3) -1.5 ±0.5 1.5 LSB(4)
DNL Differential nonlinearity(3) -0.5 ±0.2 0.5 LSB(4)
E(IO) Input offset error(3) TA = 25°C(5) -3 ±0.5 3 LSB(4)
TA = –40°C to +125°C(5) -20 ±3 20
dVOS/dT Input offset thermal drift(5) 1 μV/°C
GE Gain error(3) EN_MARG = 0b(1)(6) -0.02 ±0.005 0.02 %FSR
dGE/dT Gain error thermal drift EN_MARG = 0b(1)(6) 2.5 ppm/°C
TNS Transition noise 0.72 LSB(4)
First output code deviation for
burst-mode data acquisition		 See Reference Buffer Module –3 3 TNS
CMRR Common-mode rejection ratio dc to 20 kHz 80 dB
SAMPLING DYNAMICS
Aperture delay 4 ns
tj-rms Aperture jitter 2 ps RMS
f3-DB(small) Small-signal bandwidth 23 MHz
AC ACCURACY(2)(7) (CREFBUF = 22 µF, RESR = 1 Ω)
SINAD Signal-to-noise + distortion fIN = 2 kHz 100 102.48 dB
SNR Signal-to-noise ratio fIN = 2 kHz 101 102.5 dB
fIN = 100 kHz 99
THD Total harmonic distortion fIN = 2 kHz –125 dB
fIN = 100 kHz –110
SFDR Spurious-free dynamic range fIN = 2 kHz 125 dB
LDO OUTPUT (DECAP)
VLDO LDO output voltage
(DECAP pins)		 2.85 V
CLDO External ceramic capacitor on DECAP pins 1 µF
tPU_LDO LDO power-up time CLDO = 1 µF, RVDD> VLDO 1 ms
ISHRT-LDO Short-circuit current 100 mA
DIGITAL INPUTS
VIH High-level input voltage 1.65 V < DVDD< 2.3 V 0.8 DVDD DVDD + 0.3 V
2.3 V < DVDD< 5.5 V 0.7 DVDD DVDD + 0.3
VIL Low-level input voltage 1.65 V < DVDD< 2.3 V –0.3 0.2 DVDD V
2.3 V < DVDD< 5.5 V –0.3 0.3 DVDD
Input current ±0.01 0.1 μA
DIGITAL OUTPUTS
VOH High-level output voltage IOH = 500-µA source 0.8 DVDD DVDD V
VOL Low-level output voltage IOH = 500-µA sink 0 0.2 DVDD V
POWER SUPPLY
IRVDD Analog supply current ADS8910B at RVDD = 5 V, 1-MSPS 4.2 5.8 mA
ADS8912B at RVDD = 5 V, 500-KSPS 3.2 4 mA
ADS8914B at RVDD = 5 V, 250-KSPS 2.8 3.6 mA
Static, no conversion 970 μA
Static, PD_ADC = 1b(8) 900 μA
Static, PD_REFBUF = 1b(8) 120 μA
Static, PD_ADC = 1b and PD_REFBUF = 1b(8) 40 μA
IDVDD Digital supply current DVDD = 3 V, CLOAD = 10 pF, no conversion 1 μA
PRVDD Power dissipation ADS8910B at RVDD = 5 V, 1-MSPS 21 29 mW
ADS8912B at RVDD = 5 V, 500-KSPS 16 20
ADS8914B at RVDD = 5 V, 250-KSPS 14 18
(1) See the REF_MRG Register.
(2) While operating with internal reference buffer and LDO.
(3) See Figure 8, Figure 9, Figure 14, and Figure 15 for statistical distribution data for DNL, INL, offset, and gain error parameters.
(4) LSB = least-significant bit. 1 LSB at 18-bit resolution is approximately 3.8 ppm.
(5) For selected VREF, see the OFST_CAL Register.
(6) Includes internal reference buffer errors and drifts.
(7) For VIN = –0.1 dBFS.
(8) See the PD_CNTL Register.