JAJSCA2B June   2016  – January 2018 ADS8910B , ADS8912B , ADS8914B

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ADS89xxB内蔵の機能によりシステムを簡単に設計
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 LDO Module
      2. 7.3.2 Reference Buffer Module
      3. 7.3.3 Converter Module
        1. 7.3.3.1 Sample-and-Hold Circuit
        2. 7.3.3.2 Internal Oscillator
        3. 7.3.3.3 ADC Transfer Function
      4. 7.3.4 Interface Module
    4. 7.4 Device Functional Modes
      1. 7.4.1 RST State
      2. 7.4.2 ACQ State
      3. 7.4.3 CNV State
    5. 7.5 Programming
      1. 7.5.1 Output Data Word
      2. 7.5.2 Data Transfer Frame
      3. 7.5.3 Interleaving Conversion Cycles and Data Transfer Frames
      4. 7.5.4 Data Transfer Protocols
        1. 7.5.4.1 Protocols for Configuring the Device
        2. 7.5.4.2 Protocols for Reading From the Device
          1. 7.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols
          2. 7.5.4.2.2 SPI-Compatible Protocols with Bus Width Options
          3. 7.5.4.2.3 Source-Synchronous (SRC) Protocols
            1. 7.5.4.2.3.1 Output Clock Source Options with SRC Protocols
            2. 7.5.4.2.3.2 Bus Width Options With SRC Protocols
            3. 7.5.4.2.3.3 Output Data Rate Options With SRC Protocols
      5. 7.5.5 Device Setup
        1. 7.5.5.1 Single Device: All multiSPI Options
        2. 7.5.5.2 Single Device: Minimum Pins for a Standard SPI Interface
        3. 7.5.5.3 Multiple Devices: Daisy-Chain Topology
        4. 7.5.5.4 Multiple Devices: Star Topology
    6. 7.6 Register Maps
      1. 7.6.1 Device Configuration and Register Maps
        1. 7.6.1.1 PD_CNTL Register (address = 04h) [reset = 00h]
          1. Table 11. PD_CNTL Register Field Descriptions
        2. 7.6.1.2 SDI_CNTL Register (address = 008h) [reset = 00h]
          1. Table 12. SDI_CNTL Register Field Descriptions
        3. 7.6.1.3 SDO_CNTL Register (address = 0Ch) [reset = 00h]
          1. Table 13. SDO_CNTL Register Field Descriptions
        4. 7.6.1.4 DATA_CNTL Register (address = 010h) [reset = 00h]
          1. Table 14. DATA_CNTL Register Field Descriptions
        5. 7.6.1.5 PATN_LSB Register (address = 014h) [reset = 00h]
          1. Table 15. PATN_LSB Register Field Descriptions
        6. 7.6.1.6 PATN_MID Register (address = 015h) [reset = 00h]
          1. Table 16. PATN_MID Register Field Descriptions
        7. 7.6.1.7 PATN_MSB Register (address = 016h) [reset = 00h]
          1. Table 17. PATN_MSB Register Field Descriptions
        8. 7.6.1.8 OFST_CAL Register (address = 020h) [reset = 00h]
          1. Table 18. OFST_CAL Register Field Descriptions
        9. 7.6.1.9 REF_MRG Register (address = 030h) [reset = 00h]
          1. Table 19. REF_MRG Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ADC Reference Driver
      2. 8.1.2 ADC Input Driver
        1. 8.1.2.1 Charge-Kickback Filter
        2. 8.1.2.2 Input Amplifier Selection
    2. 8.2 Typical Application
      1. 8.2.1 Data Acquisition (DAQ) Circuit for Lowest Distortion and Noise Performance With Differential Input
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DAQ Circuit With FDA Input Driver and Single-Ended or Differential Input
      3. 8.2.3 Design Requirements
      4. 8.2.4 Detailed Design Procedure
      5. 8.2.5 Application Curves
  9. 9 Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Signal Path
      2. 10.1.2 Grounding and PCB Stack-Up
      3. 10.1.3 Decoupling of Power Supplies
      4. 10.1.4 Reference Decoupling
      5. 10.1.5 Differential Input Decoupling
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 関連リンク
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 Switching Characteristics

At RVDD = 5.5 V, DVDD = 1.65 V to 5.5 V, VREF = 5 V, and maximum throughput (unless otherwise noted).
Minimum and maximum values at TA = –40°C to +125°C; typical values at TA = 25°C.
PARAMETER MIN TYP MAX UNIT TIMING DIAGRAM
CONVERSION CYCLE
tconv Conversion time ADS8910B 580 640 ns Figure 1
ADS8912B 1100 1200
ADS8914B 2400 2500
ASYNCHRONOUS RESET, AND LOW POWER MODES
td_rst Delay time: RST rising to RVS rising 3 ms Figure 2
tPU_ADC Power-up time for converter module 1 ms See PD_CNTL Register
tPU_REFBUF Power-up time for internal reference buffer, CREFBUF = 22 µF 10 ms
tPU_Device Power-up time for device CLDO = 1 µF, CREFBUF = 22 µF 10 ms
SPI-COMPATIBLE SERIAL INTERFACE
tden_CSDO Delay time: CS falling to data enable 9 ns Figure 3
tdz_CSDO Delay time: CS rising to SDO going to Hi-Z 10 ns
td_CKDO Delay time: SCLK launch edge to (next) data valid on SDO 13 ns
td_CSRDY_f Delay time: CS falling to RVS falling 12 ns Figure 4
td_CSRDY_r Delay time:
CS rising to RVS rising		 After NOP operation 30 ns Figure 4
After WR or RD operation 120
SOURCE-SYNCHRONOUS SERIAL INTERFACE (External Clock)(1)
td_CKSTR_r Delay time: SCLK launch edge to RVS rising 13 ns Figure 4
td_CKSTR_f Delay time: SCLK launch edge to RVS falling 13 ns
toff_STRDO_f Time offset: RVS falling to (next) data valid on SDO -2 2 ns
toff_STRDO_r Time offset: RVS rising to (next) data valid on SDO -2 2 ns
tph_STR Strobe output high time, 2.35 V ≤ DVDD ≤ 5.5 V 0.45 0.55 tSTR
tpl_STR Strobe output low time, 2.35 V ≤ DVDD ≤ 5.5 V 0.45 0.55 tSTR
SOURCE-SYNCHRONOUS SERIAL INTERFACE (Internal Clock)
td_CSSTR Delay time: CS falling to RVS rising 15 50 ns Figure 5
tSTR Strobe output time period INTCLK option 15 ns
INTCLK / 2 option 30
INTCLK / 4 option 60
tph_STR Strobe output high time 0.45 0.55 tSTR
tpl_STR Strobe output low time 0.45 0.55 tSTR
ADS8910B ADS8912B ADS8914B ai_typ_conv_sbas707.gifFigure 1. Conversion Cycle Timing
ADS8910B ADS8912B ADS8914B tim_reset_sbas707.gifFigure 2. Asynchronous Reset Timing
ADS8910B ADS8912B ADS8914B tim_spi_sbas707.gif
1. The SCLK polarity, launch edge, and capture edge depend on the SPI protocol selected.
Figure 3. SPI-Compatible Serial Interface Timing
ADS8910B ADS8912B ADS8914B tim_srcsync-extclk_sbas707.gifFigure 4. Source-Synchronous Serial Interface Timing (External Clock)
ADS8910B ADS8912B ADS8914B tim_srcsync-intclk_sbas707.gifFigure 5. Source-Synchronous Serial Interface Timing (Internal Clock)