JAJSCA2B June 2016 – January 2018 ADS8910B , ADS8912B , ADS8914B
PRODUCTION DATA.
The device provides an option to increase the SDO bus width from one bit (default, single SDO) to two bits (dual SDO) or four bits (quad SDO) when operating with any of the four legacy, SPI-compatible protocols.
Set the SDO_WIDTH[1:0] bits in the SDO_CNTL register to select the SDO bus width. The SCLK launch edge depends on the SPI protocol selection (as shown in Table 7).
PROTOCOL | SCLK POLARITY
(At CS Falling Edge) |
SCLK PHASE
(Capture Edge) |
MSB BIT LAUNCH EDGE | SDI_CNTL | SDO_CNTL | #SCLK
(Optimal Read Frame) |
TIMING DIAGRAM |
---|---|---|---|---|---|---|---|
SPI-00-D | Low | Rising | CS falling | 00h | 08h | 9 | Figure 60 |
SPI-01-D | Low | Falling | First SCLK rising | 01h | 08h | 9 | Figure 61 |
SPI-10-D | High | Falling | CS falling | 02h | 08h | 9 | Figure 62 |
SPI-11-D | High | Rising | First SCLK falling | 03h | 08h | 9 | Figure 63 |
SPI-00-Q | Low | Rising | CS falling | 00h | 0Ch | 5 | Figure 64 |
SPI-01-Q | Low | Falling | First SCLK rising | 01h | 0Ch | 5 | Figure 65 |
SPI-10-Q | High | Falling | CS falling | 02h | 0Ch | 5 | Figure 66 |
SPI-11-Q | High | Rising | First SCLK falling | 03h | 0Ch | 5 | Figure 67 |
In dual-SDO mode (SDO_WIDTH[1:0] = 10b), two bits of data are launched on the two SDO pins (SDO-0 and SDO-1) on every SCLK launch edge.
In quad-SDO mode (SDO_WIDTH[1:0] = 11b), four bits of data are launched on the four SDO pins (SDO-0, SDO-1, SDO-2, and SDO-3) on every SCLK launch edge.
For SDI_MODE[1:0] = 00b or 10b, the device supports an early data launch (EDL) option. Set SDO_MODE[1:0] = 01b in the SDO_CNTL register to enable the feature (see Table 8). Setting SDO_MODE[1:0] = 01b has no effect if SDI_MODE[1:0] = 01b or 11b.
PROTOCOL | SCLK POLARITY
(At CS Falling Edge) |
SCLK PHASE
(Capture Edge) |
MSB BIT LAUNCH EDGE | SDI_CNTL | SDO_CNTL | NO. OF SCLK
(Optimal Read Frame) |
TIMING DIAGRAM |
---|---|---|---|---|---|---|---|
SPI-00-D-EDL | Low | Rising | CS falling | 00h | 09h | 9 | Figure 60 |
SPI-10-D-EDL | High | Falling | CS falling | 02h | 09h | 9 | Figure 62 |
SPI-00-Q-EDL | Low | Rising | CS falling | 00h | 0Dh | 5 | Figure 64 |
SPI-10-Q-EDL | High | Falling | CS falling | 02h | 0Dh | 5 | Figure 66 |
As shown in Figure 58, and Figure 59, the device launches the output data bits on the SDO-x pins half clock earlier compared to the standard SPI protocol.
When using any of the SPI-compatible protocols, the RVS output remains low throughout the data transfer frame; see the Timing Requirements and Switching Characteristics tables for associated timing parameters.
Figure 60 to Figure 71 illustrate how the wider data bus allows the host controller to read all 22 bits of the output data word using shorter data transfer frames. Table 7 and Table 8 show the number of SCLK required in an optimal read frame for the different output protocol selections.
NOTE
With SDO_CNTL[7:0] ≠ 00h or 01h, a long data transfer frame does not result in daisy-chain operation. On SDO pin (or pins), the 22 bits of output data word are followed by zeros.