7.3.1 LDO Module

To enable single-supply operation, the device features an internal low-dropout regulator (LDO). The LDO is powered by the RV_DD supply, and the output is available on the two DECAP pins. This LDO output powers the critical analog blocks within the device, and must not be used for any other external purposes.

Short the two DECAP pins together, and decouple with the GND pin by placing a 1-μF, X7R-grade, ceramic capacitor with a 10-V rating, as shown in Figure 32. There is no upper limit on the value of the decoupling capacitor; however, a larger decoupling capacitor results in a longer power-up time for the device. See the Layout section for layout recommendations.

Figure 32. Internal LDO Connections

7.3.2 Reference Buffer Module

On the CONVST rising edge, the device moves from ACQ state to CONV state, and the internal capacitors are switched to the REFBUFOUT pins as per the successive approximation algorithm. Most of the switching charge required during the conversion process is provided by external decoupling capacitor C_REFBUF. If the charge lost from the C_REFBUF is not replenished before the next CONVST rising edge, the voltage on REFBUFOUT pins is less than V_REFBUFOUT. The subsequent conversion occurs with this different reference voltage, and causes a proportional error in the output code. The internal reference buffer of the device maintains the voltage on REFBUFOUT pins within 0.5-LSB of V_REFBUFOUT. All the performance characteristics of the device are specified with the internal reference buffer and specified values of C_REFBUF and R_ESR.

In burst-mode of operation, the device stays in ACQ state for a long duration of time and then performs a burst of conversions. During the acquisition state (ACQ), the sampling capacitor (C_S) is connected to the differential input pins and no charge is drawn from the REFBUFOUT pins. However, during the very first conversion cycle, there is a step change in the current drawn from the REFBUFOUT pins. This sudden change in load triggers a transient settling response in the reference buffer. For a fixed input voltage, any transient settling error at the end of the conversion cycle results in a change in output codes over the subsequent conversions, as shown in Figure 33. The internal reference buffer of the ADS89xxB, when used with the recommended values of C_REFBUF and R_ESR, keeps the transient settling error at the end of each conversion cycle within 0.5-LSB. Therefore, the device supports burst-mode of operation with every conversion result being as per the datasheet specifications.

Figure 33. ADC Output Codes in Burst-Mode Operation With Various ADC Reference Buffers

Figure 34 shows the block diagram of the internal reference buffer.

Figure 34. Internal Reference Buffer Block Diagram

The input range for the device is set by the external voltage applied at the REFIN pin (V_REF). The REFIN pin has electrostatic discharge (ESD) protection diodes to the RVDD and GND pins. For minimum input offset error (see E_(IO) specified in the Electrical Characteristics), set the REF_SEL[2:0] bits to the value closest to V_REF (see the OFST_CAL register).

The internal reference buffer has a typical gain of 1 V/V with minimal offset error (see V_(RO) specified in the Electrical Characteristics), and the output of the buffer is available between the REFBUFOUT pins and the REFM pins. Set the REF_OFST[4:0] bits to add or subtract an intentional offset voltage (see the REF_MRG register).

Figure 35 shows the external connections required for the internal reference buffer.

Figure 35. External Connections for the Internal Reference Buffer

Select R_{REF_FLT} and C_{REF_FLT} to limit the broadband noise contribution from the external reference source. The device takes very little current, I_REF, from the REFIN pin (typically, 0.1 µA). However, this current flows through R_{REF_FLT} and may result in additional gain error.

Short the two REFBUFOUT pins externally. Short the two REFM pins to GND externally. As shown in Figure 35, place a combination of R_ESR and C_REFBUF (see the Electrical Characteristics) between the REFBUFOUT pins and the REFM pins as close to the device as possible. See the Layout section for layout recommendations.

7.3.3 Converter Module

As shown in Figure 36, the converter module samples the analog input signal (provided between the AINP and AINM pins), compares this signal with the reference voltage (between the pair of REFBUFOUT and REFM pins), and generates an equivalent digital output code.

The converter module receives RST and CONVST inputs from the interface module, and outputs the ADCST signal and the conversion result back to the interface module.

Figure 36. Converter Module

7.3.3.1 Sample-and-Hold Circuit

These devices support unipolar, fully differential, analog input signals. Figure 37 shows a small-signal equivalent circuit of the sample-and-hold circuit. Each sampling switch is represented by a resistance (R_S1 and R_S2, typically 50 Ω) in series with an ideal switch (SW₁ and SW₂). The sampling capacitors, C_S1 and C_S2, are typically 60 pF.

Figure 37. Input Sampling Stage Equivalent Circuit

During the acquisition process (ACQ state), both positive and negative inputs are individually sampled on C_S1 and C_S2, respectively. During the conversion process (CNV state), the device converts for the voltage difference between the two sampled values: V_AINP – V_AINM.

Each analog input pin has electrostatic discharge (ESD) protection diodes to REFBUFOUT and GND. Keep the analog inputs within the specified range to avoid turning the diodes on.

Equation 1 and Equation 2 show the full-scale input range (FSR) and common-mode voltage (V_CM), respectively, supported at the analog inputs for any external reference voltage provided on the REFIN pin (V_REF).

Equation 1.

Equation 2.

7.3.3.3 ADC Transfer Function

The device family supports unipolar, fully differential analog inputs. The device output is in two's compliment format. Figure 38 and Table 1 show the ideal transfer characteristics for the device.

The least significant bit (LSB) for the ADC is given by Equation 3:

Equation 3.

where

Figure 38. Differential Transfer Characteristics

Table 1. Transfer Characteristics

DIFFERENTIAL ANALOG INPUT VOLTAGE (AINP – AINM)	OUTPUT CODE (HEX)
< –VREF	8000
–VREF + 1 LSB	8001
–1 LSB	FFFF
0	0000
1 LSB	0001
> VREF – 1 LSB	7FFF

7.3.4 Interface Module

The interface module facilitates the communication and data transfer between the device and the host controller. As shown in Figure 39, the module consists of shift registers (both input and output), configuration registers, and a protocol unit.

Figure 39. Interface Module

The Pin Configuration and Functions section provides descriptions of the interface pins. The Data Transfer Frame section details the functions of shift registers, the SCLK counter, and the command processor. The Data Transfer Protocols section details supported protocols. The Register Maps section explains the configuration registers and bit settings.

7.4.1 RST State

The RST pin is an asynchronous digital input for the device. To enter RST state, the host controller pulls the RST pin low and keeps it low for the t_{wl_RST} duration (as specified in the Timing Requirements table).

In RST state, all configuration registers (see the Register Maps section) are reset to their default values, the RVS pin remains low, and the SDO-x pins are Hi-Z.

To exit RST state, the host controller pulls the RST pin high, with CONVST and SCLK held low and CS held high, as shown in Figure 41. After a delay of t_{d_rst}, the device enters ACQ state and the RVS pin goes high.

Figure 41. Asynchronous Reset

7.4.2 ACQ State

In ACQ state, the device acquires the analog input signal. The device enters ACQ state at power-up, when coming out of power down (See the PD Control section), after any asynchronous reset, and at the end of every conversion.

An RST falling edge takes the device from ACQ state to RST state. A CONVST rising edge takes the device from ACQ state to CNV state.

7.4.3 CNV State

The device moves from ACQ state to CNV state on a rising edge of the CONVST pin. The conversion process uses an internal clock. The device ignores any further transitions on the CONVST signal until the ongoing conversion is complete (that is, during the time interval of t_conv).

At the end of conversion, the device enters ACQ state. The cycle time for the device is given by Equation 4:

Equation 4.

Table 2. Supported Commands

7.5.1 Output Data Word

In any data transfer frame, the contents of an internal, 22-bit, output data word are shifted out on the SDO pins. The D[21:6] bits of the 22-bit output data word for any frame F + 1, are determined by:

• Value of the DATA_VAL bit applicable to frame F + 1 (see the DATA_CNTL register)
• The command issued in frame F

If a valid RD_REG command is executed in frame F, then the D[21:14] bits in frame F + 1 reflect the contents of the selected register, and the D[13:0] bits are zeros.

If the DATA_VAL bit for frame F + 1 is set to 1, then the D[21:6] bits in frame F + 1 are replaced by the DATA_PATN[15:0] bits.

For all other combinations, the D[21:6] bits for frame F + 1 are the latest conversion result.

Figure 43 shows the output data word. Figure 44 shows further details of the parity computation unit illustrated in Figure 43.

Figure 43. Output Data Word (D[21:0])

Figure 44. Parity Bits Computation

With the PAR_EN bit set to 0, the D[5] and D[4] bits of the output data word are set to 0 (default configuration).

When the PAR_EN bit is set to 1, the device calculates the parity bits (FLPAR and FTPAR) and appends them as bits D[5] and D[4].

• FLPAR is the even parity calculated on bits D[21:6].
• FTPAR is the even parity calculated on the bits defined by FPAR_LOC[1:0].

See the DATA_CNTL register for more details on the FPAR_LOC[1:0] bit settings. Bits D[3:0] are set to 0000b.

7.5.2 Data Transfer Frame

A data transfer frame between the device and the host controller is bounded between a CS falling edge and the subsequent CS rising edge. The host controller can initiate a data transfer frame (as shown in Figure 45) at any time irrespective of the status of the CONVST signal; however, the data read during such a data transfer frame is a function of relative timing between the CONVST and CS signals.

Figure 45. Data Transfer Frame

For this discussion, assume that the CONVST signal remains low.

A typical data transfer frame F follows this order:

1. The host controller pulls CS low to initiate a data transfer frame. On the CS falling edge:
   • RVS goes low, indicating the beginning of the data transfer frame.
   • The SCLK counter is reset to 0.
   • The device takes control of the data bus. As shown in Figure 45, the 22-bit contents of the output data word (see Figure 43) are loaded in to the 22-bit output data register (ODR; see Figure 39).
   • The 22-bit input data register (IDR; see Figure 39) is reset to 000000h, corresponding to a NOP command.
2. During the frame, the host controller provides clocks on the SCLK pin. Inside the device:
   • For each SCLK capture edge, the SCLK counter is incremented and the data bit received on the SDI pin is shifted in to the IDR.
   • For each launch edge of the output clock (SCLK in this case), ODR data are shifted out on the selected SDO-x pins.
   • The status of the RVS pin depends on the output protocol selection (see the Protocols for Reading From the Device section).
3. The host controller pulls CS high to end the data transfer frame. On the CS rising edge:
   • The SDO-x pins go to Hi-Z.
   • RVS goes high (after a delay of t_{d_CSRDY_r}).
   • As illustrated in Figure 45, the 22-bit contents of the IDR are transferred to the command processor (see Figure 39) for decoding and further action.

After pulling CS high, the host controller monitors for a low-to-high transition on the RVS pin, or waits for the t_{d_CSRDY_r} time (see the Switching Characteristics table) to elapse before initiating a new operation (data transfer or conversion). The delay, t_{d_CSRDY_r}, for any data transfer frame F varies based on the data transfer operation executed in frame F.

At the end of data transfer frame F:

• If the SCLK counter is < 22, then the IDR captured less than 22 bits from the SDI. In this case, the device treats frame F as a short command frame. At the end of a short command frame, the IDR is not updated and the device treats the frame as a no operation (NOP) command.
• If the SCLK counter = 22, then the IDR captured exactly 22 bits from SDI. In this case, the device treats the frame F as a optimal command frame. At the end of an optimal command frame, the command processor decodes the 22-bit contents of the IDR as a valid command word.
• If the SCLK counter > 22, then the IDR captured more than 22 bits from the SDI; however, only the last 22 bits are retained. In this case, the device treats frame F as a long command frame. At the end of a long command frame, the command processor treats the 22-bit contents of the IDR as a valid command word. There is no restriction on the maximum number of clocks that can be provided within any data transfer frame F. However, as explained above, make sure that the last 22 bits shifted into the device before the CS rising edge constitute the desired command.

In a short command frame, the write operation to the device is invalidated; however, the output data bits transferred during the short command frame are still valid output data. Therefore, the host controller can use such shorter data transfer frames to read only the required number of MSB bits from the 22-bit output data word. As shown in Figure 43, an optimal read frame for the ADS892xB devices must read only the 16 MSB bits of the output data word. The length of an optimal read frame depends on the output protocol selection; see the Protocols for Reading From the Device section for more details.

7.5.3 Interleaving Conversion Cycles and Data Transfer Frames

The host controller operates the device at the desired throughput by interleaving the conversion cycles and the data transfer frames.

The cycle time of the device, t_cycle, is the time difference between two consecutive CONVST rising edges provided by the host controller. The response time of the device, t_resp, is the time difference between the host controller initiating conversion C, and the host controller receiving the complete result for conversion C.

Figure 46 shows three conversion cycles: C, C + 1, and C + 2. Conversion C is initiated by a CONVST rising edge at time t = 0, and the conversion result becomes available for data transfer at t_conv. However, this result is loaded into the ODR only on the subsequent CS falling edge. This CS falling edge must be provided before the completion of conversion C + 1 (that is, before t_cycle + t_conv).

To achieve the rated performance specifications, the host controller must make sure that no digital signals toggle during the quiet acquisition time (t_{qt_acq}) and quiet aperture time (t_{d_cnvcap}). Any noise during t_{d_cnvcap} may negatively affect the result of the ongoing conversion, whereas any noise during t_{qt_acq} may negatively affect the result of the subsequent conversion.

Figure 46. Data Transfer Zones

This architecture allows for two distinct time zones (zone 1 and zone 2) to transfer data for each conversion. Zone 1 and zone 2 for conversion C are defined in Table 3.

Table 3. Data Transfer Zones Timing

ZONE	STARTING TIME	ENDING TIME
Zone 1 for conversion C
Zone 2 for conversion C

The response time includes the conversion time and the data transfer time, and thus is a function of the selected data transfer zone.

Figure 47 and Figure 48 illustrate interleaving of three conversion cycles (C, C + 1, and C + 2) with three data transfer frames (F, F + 1, and F + 2) in zone 1 and in zone 2, respectively.

Figure 47. Zone 1 Data Transfer

Figure 48. Zone 2 Data Transfer

To achieve cycle time t_cycle, the read time in zone 1 is given by Equation 5:

Equation 5.

For an optimal data transfer frame, Equation 5 results in an SCLK frequency given by Equation 6:

Equation 6.

Then, the zone 1 data transfer achieves a response time defined by Equation 7:

Equation 7.

At lower SCLK speeds, t_read-Z1 increases, resulting in slower response times and higher cycle times.

To achieve the same cycle time, t_cycle, the read time in zone 2 is given by Equation 8:

Equation 8.

For an optimal data transfer frame, Equation 8 results in an SCLK frequency given by Equation 9:

Equation 9.

Then, the zone 2 data transfer achieves a response time defined by Equation 10:

Equation 10.

Any increase in t_read-Z2 increases response time and may increase cycle time.

For a given cycle time, the zone 1 data transfer clearly achieves faster response time, but also requires a higher SCLK speed (as evident from Equation 5, Equation 6, and Equation 7); whereas, the zone 2 data transfer clearly requires a lower SCLK speed but has a slower response time (as evident from Equation 8, Equation 9, and Equation 10).

7.5.4 Data Transfer Protocols

This device family features a multiSPI digital interface that allows the host controller to operate at slower SCLK speeds and still achieve the required throughput and response time. The multiSPI digital interface module offers three options to reduce the SCLK speed required for data transfer:

• Increase the width of the output data bus.
• Enable double data rate (DDR) transfer.
• Extended data transfer window, as shown in Figure 48.

These three options can be combined to achieve further reduction in SCLK speed.

There are various factors that limit the maximum SCLK frequency in a system.

Figure 49 shows the delays in the communication channel between the host controller and the device in a typical serial communication.

Figure 49. Delays in Serial Communication

For example, if t_{pcb_CK} and t_{pcb_SDO} are the delays introduced by the printed circuit board (PCB) traces for the serial clock and SDO signals, t_{d_CKDO} is the clock-to-data delay of the device, t_{d_ISO} is the propagation delay introduced by the digital isolator, and t_{su_h} is the setup time specification of the host controller, then the total delay in the path is given by Equation 11:

Equation 11.

In a standard SPI protocol, the host controller and the device launch and capture data bits on alternate SCLK edges. Therefore, the t_{d_total_serial} delay must be kept to less than half of the SCLK duration. Equation 12 shows the fastest clock allowed by the SPI protocol:

Equation 12.

Larger values of the t_{d_total_serial} delay restricts the maximum SCLK speed for the SPI protocol, resulting in higher read and response times, and can possibly limit the throughput.

Figure 50 shows a delay (t_{d_delcap}) introduced in the capture path (inside the host controller).

Figure 50. Delayed Capture

The total delay in the path modifies to Equation 13:

Equation 13.

This reduction in total delay allows the SPI protocol to operate at higher clock speeds.

The multiSPI digital interface module offers two additional options to remove the restriction on the SCLK speed:

• Early data launch (EDL) mode of operation

In EDL mode, the device launches the output data on SDO-x pin (or pins) half a clock earlier compared to the standard SPI protocol. Therefore, Equation 12 modifies to Equation 14:

Equation 14.

The reduction in total delay allows the serial interface to operate at higher clock speeds.

• ADC-Clock-Master (source-synchronous) mode of operation

As illustrated in Figure 51, in ADC-Clock-Master mode, the device provides a synchronous output clock (on the RVS pin) along with the output data (on the SDO-x pins).

Figure 51. Delays in ADC-Clock-Master (Source-Synchronous) Mode

For negligible values of t_{off_STRDO}, the total delay in the path for a source-synchronous data transfer, is given by Equation 15:

Equation 15.

As shown by the difference between Equation 11 and Equation 15, using ADC-Clock-Master mode completely eliminates the effect of isolator delays (t_{d_ISO}) and clock-to-data delays (t_{d_CKDO}); typically, the largest contributors in the overall delay computation.

Furthermore, the actual values of t_{pcb_RVS} and t_{pcb_SDO} do not matter. In most cases, the t_{d_total_srcsync} delay can be kept at a minimum by routing the RVS and SDO lines together on the PCB. Therefore, the ADC-Clock-Master mode allows the data transfer between the host controller and the device to operate at much higher SCLK speeds.

7.5.4.1 Protocols for Configuring the Device

As shown in Table 4, the host controller can use any of the four legacy, SPI-compatible protocols (SPI-00-S, SPI-01-S, SPI-10-S, or SPI-11-S) to write data to the device.

Table 4. SPI Protocols for Configuring the Device

PROTOCOL	SCLK POLARITY (At CS Falling Edge)	SCLK PHASE (Capture Edge)	SDI_CNTL	SDO_CNTL	NO. OF SCLK (Optimal Command Frame)	TIMING DIAGRAM
SPI-00-S	Low	Rising	00h	00h	22	Figure 52
SPI-01-S	Low	Falling	01h	00h	22	Figure 53
SPI-10-S	High	Falling	02h	00h	22	Figure 54
SPI-11-S	High	Rising	03h	00h	22	Figure 55

At power-up or after coming out of any asynchronous reset, the device supports the SPI-00-S protocol for data-read and data-write operations.

To select a different SPI-compatible protocol, program the SDI_MODE[1:0] bits in the SDI_CNTL register. This first write operation must adhere to the SPI-00-S protocol. Any subsequent data transfer frames must adhere to the newly selected protocol.

Figure 52 to Figure 55 detail the four protocols using an optimal command frame; see the Timing Requirements and Switching Characteristics tables for associated timing parameters.

NOTE

As explained in the Data Transfer Frame section, a valid write operation to the device requires a minimum of 22 SCLKs to be provided within a data transfer frame.

Any data write operation to the device must continue to follow the SPI-compatible protocol selected in the SDI_CNTL register, irrespective of the protocol selected for the data-read operation.

Figure 52. SPI-00-S Protocol, Optimal Command Frame

Figure 54. SPI-10-S Protocol, Optimal Command Frame

Figure 53. SPI-01-S Protocol, Optimal Command Frame

Figure 55. SPI-11-S Protocol, Optimal Command Frame

7.5.4.2 Protocols for Reading From the Device

The protocols for the data-read operation can be broadly classified into three categories:

1. Legacy, SPI-compatible (SPI-xy-S) protocol
2. SPI-compatible protocols with bus width options (SPI-xy-D and SPI-xy-Q)
3. Source-synchronous (SRC) protocols

7.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols

As shown in Table 5, the host controller can use any of the four legacy, SPI-compatible protocols (SPI-00-S, SPI-01-S, SPI-10-S, or SPI-11-S) to read data from the device.

Table 5. SPI Protocols for Reading From the Device

PROTOCOL	SCLK POLARITY (At CS Falling Edge)	SCLK PHASE (Capture Edge)	MSB BIT LAUNCH EDGE	SDI_CNTL	SDO_CNTL	NO. OF SCLK (Optimal Read Frame)	TIMING DIAGRAM
SPI-00-S	Low	Rising	CS falling	00h	00h	16	Figure 56
SPI-01-S	Low	Falling	1st SCLK rising	01h	00h	16	Figure 57
SPI-10-S	High	Falling	CS falling	02h	00h	16	Figure 58
SPI-11-S	High	Rising	1st SCLK falling	03h	00h	16	Figure 59

At power-up or after coming out of any asynchronous reset, the device supports the SPI-00-S protocol for data-read and data-write operations. To select a different SPI-compatible protocol for both the data transfer operations:

1. Program the SDI_MODE[1:0] bits in the SDI_CNTL register. This first write operation must adhere to the SPI-00-S protocol. Any subsequent data transfer frames must adhere to the newly selected protocol.
2. Set the SDO_MODE[1:0] bits = 00b in the SDO_CNTL register.

Figure 56 to Figure 59 explain the details of the four protocols using an optimal command frame to read all 22 bits of the output data word. Table 5 shows the number of SCLK required in an optimal read frame for the different output protocol selections.

Figure 56. SPI-00-S Protocol, 22 SCLKs

Figure 58. SPI-10-S Protocol, 22 SCLKs

Figure 57. SPI-01-S Protocol, 22 SCLKs

Figure 59. SPI-11-S Protocol, 22 SCLKs

For SDI_MODE[1:0] = 00b or 10b, the device supports an Early Data Launch (EDL) option. Set SDO_MODE[1:0] = 01b in the SDO_CNTL register to enable the feature (see Table 6). Setting SDO_MODE[1:0] = 01b has no effect if SDI_MODE[1:0] = 01b or 11b.

Table 6. SPI Protocols with Early Data Launch

PROTOCOL	SCLK POLARITY (At CS Falling Edge)	SCLK PHASE (Capture Edge)	MSB BIT LAUNCH EDGE	SDI_CNTL	SDO_CNTL	NO. OF SCLK (Optimal Read Frame)	TIMING DIAGRAM
SPI-00-S-EDL	Low	Rising	CS falling	00h	01h	16	Figure 56
SPI-10-S-EDL	High	Falling	CS falling	02h	01h	16	Figure 58

As shown in Figure 60, and Figure 61, the device launches the output data bit on the SDO-0 pin half clock earlier compared to the standard SPI protocol.

Figure 60. SPI-00-S-EDL Protocol, 22 SCLKs

Figure 61. SPI-10-S-EDL Protocol, 22 SCLKs

When using these SPI-compatible protocols, the RVS output remains low throughout the data transfer frame; see the Timing Requirements and Switching Characteristics tables for associated timing parameters.

With SDO_CNTL[7:0] = 00h or 01h, if the host controller uses a long data transfer frame, the device exhibits daisy-chain operation (see the Multiple Devices: Daisy-Chain Topology section).

NOTE

Use SPI-compatible protocols to execute the RD_REG, WR_REG, CLR_BITS, and SET_BITS commands specified in Table 2.

7.5.4.2.2 SPI-Compatible Protocols with Bus Width Options

The device provides an option to increase the SDO bus width from one bit (default, single SDO) to two bits (dual SDO) or four bits (quad SDO) when operating with any of the four legacy, SPI-compatible protocols.

Set the SDO_WIDTH[1:0] bits in the SDO_CNTL register to select the SDO bus width. The SCLK launch edge depends on the SPI protocol selection (as shown in Table 7).

Table 7. SPI-Compatible Protocols with Bus Width Options

PROTOCOL	SCLK POLARITY (At CS Falling Edge)	SCLK PHASE (Capture Edge)	MSB BIT LAUNCH EDGE	SDI_CNTL	SDO_CNTL	#SCLK (Optimal Read Frame)	TIMING DIAGRAM
SPI-00-D	Low	Rising	CS falling	00h	08h	8	Figure 62
SPI-01-D	Low	Falling	First SCLK rising	01h	08h	8	Figure 63
SPI-10-D	High	Falling	CS falling	02h	08h	8	Figure 64
SPI-11-D	High	Rising	First SCLK falling	03h	08h	8	Figure 65
SPI-00-Q	Low	Rising	CS falling	00h	0Ch	4	Figure 66
SPI-01-Q	Low	Falling	First SCLK rising	01h	0Ch	4	Figure 67
SPI-10-Q	High	Falling	CS falling	02h	0Ch	4	Figure 68
SPI-11-Q	High	Rising	First SCLK falling	03h	0Ch	4	Figure 69

In dual-SDO mode (SDO_WIDTH[1:0] = 10b), two bits of data are launched on the two SDO pins (SDO-0 and SDO-1) on every SCLK launch edge.

In quad-SDO mode (SDO_WIDTH[1:0] = 11b), four bits of data are launched on the four SDO pins (SDO-0, SDO-1, SDO-2, and SDO-3) on every SCLK launch edge.

Figure 62. SPI-00-D Protocol

Figure 64. SPI-10-D Protocol

Figure 66. SPI-00-Q Protocol

Figure 68. SPI-10-Q Protocol

Figure 63. SPI-01-D Protocol

Figure 65. SPI-11-D Protocol

Figure 67. SPI-01-Q Protocol

Figure 69. SPI-11-Q Protocol

For SDI_MODE[1:0] = 00b or 10b, the device supports an early data launch (EDL) option. Set SDO_MODE[1:0] = 01b in the SDO_CNTL register to enable the feature (see Table 8). Setting SDO_MODE[1:0] = 01b has no effect if SDI_MODE[1:0] = 01b or 11b.

Table 8. SPI Protocols with Early Data Launch

PROTOCOL	SCLK POLARITY (At CS Falling Edge)	SCLK PHASE (Capture Edge)	MSB BIT LAUNCH EDGE	SDI_CNTL	SDO_CNTL	NO. OF SCLK (Optimal Read Frame)	TIMING DIAGRAM
SPI-00-D-EDL	Low	Rising	CS falling	00h	09h	8	Figure 62
SPI-10-D-EDL	High	Falling	CS falling	02h	09h	8	Figure 64
SPI-00-Q-EDL	Low	Rising	CS falling	00h	0Dh	4	Figure 66
SPI-10-Q-EDL	High	Falling	CS falling	02h	0Dh	4	Figure 68

As shown in Figure 60, and Figure 61, the device launches the output data bits on the SDO-x pins half clock earlier compared to the standard SPI protocol.

Figure 70. SPI-00-D-EDL Protocol

Figure 72. SPI-00-Q-EDL Protocol

Figure 71. SPI-10-D-EDL Protocol

Figure 73. SPI-10-Q-EDL Protocol

When using any of the SPI-compatible protocols, the RVS output remains low throughout the data transfer frame; see the Timing Requirements and Switching Characteristics tables for associated timing parameters.

Figure 62 to Figure 73 illustrate how the wider data bus allows the host controller to read all 22 bits of the output data word using shorter data transfer frames. Table 7 and Table 8 show the number of SCLK required in an optimal read frame for the different output protocol selections.

NOTE

With SDO_CNTL[7:0] ≠ 00h or 01h, a long data transfer frame does not result in daisy-chain operation. On SDO pin (or pins), the 22 bits of output data word are followed by zeros.

7.5.4.2.3 Source-Synchronous (SRC) Protocols

As described in the Data Transfer Protocols section, the multiSPI digital interface supports an ADC-Clock-Master or a source-synchronous mode of data transfer between the device and host controller. In this mode, the device provides an output clock that is synchronous with the output data. Furthermore, the host controller can also select the output clock source, data bus width, and data transfer rate.

7.5.4.2.3.1 Output Clock Source Options with SRC Protocols

In all SRC protocols, the RVS pin provides the output clock. The device allows this output clock to be synchronous to either the external clock provided on the SCLK pin or to the internal clock of the device. Furthermore, this internal clock can be divided by a factor of two or four to lower the data rates.

As shown in Figure 74, set the SSYNC_CLK_SEL[1:0] bits in the SDO_CNTL register to select the output clock source.

Figure 74. Output Clock Source Options With SRC Protocols

7.5.4.2.3.2 Bus Width Options With SRC Protocols

The device provides an option to increase the SDO bus width from one bit (default, single SDO) to two bits (dual SDO) or to four bits (quad SDO) when operating with any of the SRC protocols. Set the SDO_WIDTH[1:0] bits in the SDO_CNTL register to select the SDO bus width.

In dual-SDO mode (SDO_WIDTH[1:0] = 10b), two bits of data are launched on the two SDO pins (SDO-0 and SDO-1) on every SCLK rising edge.

In quad-SDO mode (SDO_WIDTH[1:0] = 11b), four bits of data are launched on the four SDO pins (SDO-0, SDO-1, SDO-2, and SDO-3) on every SCLK rising edge.

7.5.4.2.3.3 Output Data Rate Options With SRC Protocols

The device provides an option to transfer the data to the host controller at a single data rate (default, SDR) or at a double data rate (DDR). Set the DATA_RATE bit in the SDO_CNTL register to select the data transfer rate.

In SDR mode (DATA_RATE = 0b), the RVS pin toggles from low to high, and the output data bits are launched on the SDO pins on the output clock rising edge.

In DDR mode (DTA_RATE = 1b), the RVS pin toggles (from low-to-high or high-to-low), and the output data bits are launched on the SDO pins on every output clock edge, starting with the first rising edge.

The device supports all 24 combinations of output clock source, bus width, and output data rate, as shown in Table 9.

Table 9. SRC Protocol Combinations

PROTOCOL	OUTPUT CLOCK SOURCE	BUS WIDTH	OUTPUT DATA RATE	SDI_CNTL	SDO_CNTL	#OUTPUT CLOCK (Optimal Read Frame)	TIMING DIAGRAM
SRC-EXT-SS	SCLK(3)	Single	SDR	00h, 01h, 02h, or 03h(1)	03h	8	Figure 75
SRC-INT-SS	INTCLK(2)	Single	SDR		43h	8	Figure 76
SRC-IB2-SS	INTCLK / 2(2)	Single	SDR		83h	8
SRC-IB4-SS	INTCLK / 4(2)	Single	SDR		C3h	8
SRC-EXT-DS	SCLK(3)	Dual	SDR		0Bh	8	Figure 79
SRC-INT-DS	INTCLK(2)	Dual	SDR		4Bh	8	Figure 80
SRC-IB2-DS	INTCLK / 2(2)	Dual	SDR		8Bh	8
SRC-IB4-DS	INTCLK / 4(2)	Dual	SDR		CBh	8
SRC-EXT-QS	SCLK(3)	Quad	SDR		0Fh	4	Figure 83
SRC-INT-QS	INTCLK(2)	Quad	SDR		4Fh	4	Figure 84
SRC-IB2-QS	INTCLK / 2(2)	Quad	SDR		8Fh	4
SRC-IB4-QS	INTCLK / 4(2)	Quad	SDR		CFh	4
SRC-EXT-SD	SCLK(3)	Single	DDR		13h	8	Figure 77
SRC-INT-SD	INTCLK(2)	Single	DDR		53h	8	Figure 78
SRC-IB2-SD	INTCLK / 2(2)	Single	DDR		93h	8
SRC-IB4-SD	INTCLK / 4(2)	Single	DDR		D3h	8
SRC-EXT-DD	SCLK(3)	Dual	DDR		1Bh	4	Figure 81
SRC-INT-DD	INTCLK(2)	Dual	DDR		5Bh	4	Figure 82
SRC-IB2-DD	INTCLK / 2(2)	Dual	DDR		9Bh	4
SRC-IB4-DD	INTCLK / 4(2)	Dual	DDR		DBh	4
SRC-EXT-QD	SCLK(3)	Quad	DDR		1Fh	2	Figure 85
SRC-INT-QD	INTCLK(2)	Quad	DDR		5Fh	2	Figure 86
SRC-IB2-QD	INTCLK / 2(2)	Quad	DDR		9Fh	2
SRC-IB4-QD	INTCLK / 4(2)	Quad	DDR		DFh	2

(1) Any of the four values can be used; see the Protocols for Configuring the Device section for more information.

(2) The device supports INTCLK, INTCLK / 2, and INTCLK / 4 options only for data transfer operations in zone 1. The EXTCLK option is supported in zone 1 and zone 2; see Figure 46.

(3) The EXTCLK option is not recommended when operating with DV_DD < 2.35 V.

Figure 75 to Figure 86 show the details of various source synchronous protocols. Table 9 shows the number of output clocks required in an optimal read frame for the different output protocol selections.

Figure 75. SRC-EXT-SS: SRC, SCLK, Single SDO, SDR

Figure 77. SRC-EXT-SD: SRC, SCLK, Single SDO, DDR

Figure 79. SRC-EXT-DS: SRC, SCLK, Dual SDO, SDR

Figure 76. SRC-INT-SS: SRC, INTCLK, Single SDO, SDR

Figure 78. SRC-INT-SD: SRC, INTCLK, Single SDO, DDR

Figure 80. SRC-INT-DS: SRC, INTCLK, Dual SDO, SDR

Figure 81. SRC-EXT-DD: SRC, SCLK, Dual SDO, DDR

Figure 83. SRC-EXT-QS: SRC, SCLK, Quad SDO, SDR

Figure 85. SRC-EXT-QD: SRC, SCLK, Quad SDO, DDR

Figure 82. SRC-INT-DD: SRC, INTCLK, Dual SDO, DDR

Figure 84. SRC-INT-QS: SRC, INTCLK, Quad SDO, SDR

Figure 86. SRC-INT-QD: SRC, INTCLK, Quad SDO, DDR

7.5.5 Device Setup

The multiSPI digital interface and the device configuration registers offer multiple operation modes. This section describes how to select the hardware connection topology to meet different system requirements.

7.5.5.1 Single Device: All multiSPI Options

Figure 87 shows the connections between a host controller and a single device in order to exercise all options provided by the multiSPI digital interface.

Figure 87. MultiSPI Digital Interface, All Pins

7.5.5.2 Single Device: Minimum Pins for a Standard SPI Interface

Figure 88 shows the minimum-pin interface for applications using a standard SPI protocol.

Figure 88. SPI Interface, Minimum Pins

The CS, SCLK, SDI, and SDO-0 pins constitute a standard SPI port of the host controller. The CONVST pin is tied to CS, and the RST pin is tied to DVDD. The SDO-1, SDO-2, and SDO-3 pins have no external connections. The following features are also available:

• Control the CONVST pin independently to get additional timing flexibility.
• Control RST pin independently to add asynchronous reset functionality.
• Monitor the RVS pin for additional timing benefits.

7.5.5.3 Multiple Devices: Daisy-Chain Topology

A typical connection diagram showing multiple devices in a daisy-chain topology is shown in Figure 89.

Figure 89. Daisy-Chain Connections

The CONVST, CS, and SCLK inputs of all devices are connected together and controlled by a single CONVST, CS, and SCLK pin of the host controller, respectively. The SDI input pin of the first device in the chain (Device 1) is connected to the SDO pin of the host controller, the SDO-0 output pin of Device 1 is connected to the SDI input pin of Device 2, and so on. The SDO-0 output pin of the last device in the chain (Device N) is connected to the SDI pin of the host controller.

To operate multiple devices in a daisy-chain topology, the host controller sets the configuration registers in each device with identical values and operates with any of the legacy, SPI-compatible protocols for data-read and data-write operations (SDO_CNT[7:0] = 00h or 01h). With these configurations settings, the 22-bit ODR and 22-bit IDR registers in each device collapse to form a single, 22-bit unified shift register (USR) per device, as shown in Figure 90.

Figure 90. Unified Shift Register

All devices in the daisy-chain topology sample the respective device analog input signals on the CONVST rising edge. The data transfer frame starts with a CS falling edge. On each SCLK launch edge, every device in the chain shifts out the MSB of the respective USR on to the respective SDO-0 pin. On every SCLK capture edge, each device in the chain shifts in data received on the respective SDI pin as the LSB bit of the respective USR. Therefore, in a daisy-chain configuration, the host controller receives the data of Device N, followed by the data of Device N – 1, and so on (MSB-first). On the CS rising edge, each device decodes the contents in the respective USR, and takes appropriate action.

A typical timing diagram for three devices connected in daisy-chain topology using the SPI-00-S protocol is shown in Figure 91.

Figure 91. Three-Device, Daisy-Chain Timing

In daisy-chain topology, the overall throughput of the system is proportionally reduced as more devices are connected in the daisy-chain.

NOTE

For N devices connected in daisy-chain topology, an optimal data transfer frame must contain 22 × N SCLK capture edges. For a longer data transfer frame (number of SCLK in the frame > 22 × N), the host controller must appropriately align the configuration data for each device before bringing CS high. A shorter data transfer frame (number of SCLK in the frame < 22 × N) might result in an erroneous device configuration, and must be avoided.

7.5.5.4 Multiple Devices: Star Topology

A typical connection diagram showing multiple devices in a star topology is shown in Figure 92. The CONVST, SDI, and SCLK inputs of all devices are connected together, and are controlled by a single CONVST, SDO, and SCLK pin of the host controller, respectively. Similarly, the SDO output pin of all devices are tied together and connected to the a single SDI input pin of the host controller. The CS input pin of each device is individually controlled by separate CS control lines from the host controller.

Figure 92. Star-Topology Connection

The timing diagram for three devices connected in the star topology is shown in Figure 93. In order to avoid any conflict related to multiple devices driving the SDO line at the same time, make sure that the host controller pulls down the CS signal for only one device at any particular time.

Figure 93. Three-Device, Star Connection Timing

7.6.1 Device Configuration and Register Maps

The device features nine configuration registers, mapped as described in Table 10.

7.6.1.7 PATN_MSB Register (address = 016h) [reset = 00h]

This register controls the four MSB of the output pattern when DATA_VAL = 1b; see Figure 101.

Figure 100. PATN_MSB Register

7	6	5	4	3	2	1	0
0	0	0	0	PATN_MSB_BITS
R-0b	R-0b	R-0b	R-0b	R/W-0000b

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17. PATN_MSB Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	0	R	0000b	Reserved bits. Reads return 0000b.
3-0	PATN_MSB_BITS	R/W	0000b	4 MSB of the output pattern

Figure 101. DATA_PATN[15:0]