JAJSQE1 October   2024 ADS9212

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
        1. 6.3.1.1 Input Clamp Protection Circuit
        2. 6.3.1.2 Programmable Gain Amplifier (PGA)
        3. 6.3.1.3 Wide-Common-Mode Voltage Rejection Circuit
        4. 6.3.1.4 Gain Error Calibration
      2. 6.3.2 ADC Transfer Function
      3. 6.3.3 ADC Sampling Clock Input
      4. 6.3.4 Reference
        1. 6.3.4.1 Internal Reference Voltage
        2. 6.3.4.2 External Reference Voltage
      5. 6.3.5 Data Interface
        1. 6.3.5.1 Data Clock Output
        2. 6.3.5.2 ADC Output Data Randomizer
        3. 6.3.5.3 Test Patterns for Data Interface
          1. 6.3.5.3.1 Fixed Pattern
          2. 6.3.5.3.2 Digital Ramp
          3. 6.3.5.3.3 Alternating Test Pattern
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power-Down
      2. 6.4.2 Reset
      3. 6.4.3 Initialization Sequence
      4. 6.4.4 Normal Operation
    5. 6.5 Programming
      1. 6.5.1 Register Write
      2. 6.5.2 Register Read
      3. 6.5.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration
        1. 6.5.3.1 Register Write With Daisy-Chain
        2. 6.5.3.2 Register Read With Daisy-Chain
  8. 7 Register Map
    1. 7.1 Register Bank 0
    2. 7.2 Register Bank 1
    3. 7.3 Register Bank 2
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Parametric Measurement Unit (PMU)
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

Figure 4-1 RSH Package,56-Pin VQFN(Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
AINM_A 4 AI Analog input for ADC A, negative input.
AINP_A 3 AI Analog input ADC A, positive input.
AINM_B 12 AI Analog input ADC B, negative input.
AINP_B 11 AI Analog input ADC B, positive input.
AVDD_5V 15, 56 P 5V analog supply. Connect 1µF and 0.1µF decoupling capacitor to AGND.
CS 25 DI Chip-select input for configuration of SPI interface; active low. This pin has an internal 100kΩ pullup resistor to the digital interface supply.
D0 34 DO Serial output data lane 0.
D1 35 DO Serial data output lane 1.
D2 36 DO Serial data output lane 2.
D3 37 DO Serial data output lane 3.
DCLKOUT 33 DO Clock output for the data interface.
DVDD_1V8 22, 47, 48 P Digital supply pin. Connect 1µF and 0.1µF decoupling capacitors to DGND.
FCLKOUT 40 DO Frame synchronization output for data interface.
GND 1, 2, 5, 6, 7, 9, 10, 13, 14, 16, 17, 23, 46, 54, 55 P Ground.
IOGND 29, 42 P Digital interface ground. Connect to GND.
IOVDD 30, 41 P Digital I/O supply for the data interface. Connect 1µF and 0.1µF decoupling capacitors to IOGND.
NC 20, 38, 39, 45, 50, 51 — Not connected. No external connection.
PWDN 32 DI Power-down control; active low. This pin has an internal 100kΩ pullup resistor to the digital interface supply.
REFIO 52 AI/AO This pin acts as an internal reference output when the internal reference is enabled. This pin functions as an input pin for the external reference when internal reference is disabled. Connect a 10µF decoupling capacitor to the REFM pins.
REFM 8, 18, 53 AI Reference ground potential. Connect to GND.
REFOUT_2V5 19 AO 2.5V reference output. Connect a decoupling 10µF capacitor to the REFM pins.
RESET 31 DI Reset input for the device; active low. This pin has an internal 100kΩ pullup resistor to the digital interface supply.
SCLK 26 DI Serial clock input for the configuration interface. This pin has an internal 100kΩ pulldown resistor to the digital interface ground.
SDI 27 DI This pin is a multifunction logic input; pin function is determined by the SPI_EN pin. This pin has an internal 100kΩ pulldown resistor to IOGND.
SPI_EN = 0b: This pin is the logic input to select between the internal or external reference. Connect this pin to IOGND for the external reference. Connect this pin to IOVDD for the internal reference.
SPI_EN = 1b: Serial data input for the configuration interface.
SDO 28 DO Serial data output for the configuration interface.
SMPL_CLKP 44 DI Single-ended ADC sampling clock input. This pin is the positive input for the differential ADC sampling clock.
SMPL_CLKM 43 DI Connect this pin to GND for a single-ended ADC sampling clock input. This pin is the negative input for the differential ADC sampling clock.
SPI_EN 24 DI Logic input to enable the configuration SPI interface (CS, SCLK, SDI, and SDO). This pin has internal 100kΩ pullup resistor to the digital interface supply.
VDD_1V8 21, 22, 47, 48, 49 P 1.8V power-supply. Connect 1µF and 0.1µF decoupling capacitors to GND.
Thermal pad — P Exposed thermal pad; connect to AGND.
(1) I = input, O = output, I/O = input or output, G = ground, and P = power.