JAJSP59B January   2023  – May 2024 ADS9218 , ADS9219

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Thermal Information
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements
    7. 5.7  Switching Characteristics
    8. 5.8  Timing Diagrams
    9. 5.9  Typical Characteristics: All Devices
    10. 5.10 Typical Characteristics: ADS9219
    11. 5.11 Typical Characteristics: ADS9218
    12. 5.12 Typical Characteristics: ADS9217
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
      2. 6.3.2 Analog Input Bandwidth
      3. 6.3.3 ADC Transfer Function
      4. 6.3.4 Reference Voltage
      5. 6.3.5 Temperature Sensor
      6. 6.3.6 Data Averaging
      7. 6.3.7 Digital Down Converter
      8. 6.3.8 Data Interface
        1. 6.3.8.1 Data Frame Width
        2. 6.3.8.2 Synchronizing Multiple ADCs
        3. 6.3.8.3 Test Patterns for Data Interface
          1. 6.3.8.3.1 Fixed Pattern
          2. 6.3.8.3.2 Alternating Test Pattern
          3. 6.3.8.3.3 Digital Ramp
      9. 6.3.9 ADC Sampling Clock Input
    4. 6.4 Device Functional Modes
      1. 6.4.1 Reset
      2. 6.4.2 Power-Down Options
      3. 6.4.3 Normal Operation
      4. 6.4.4 Initialization Sequence
    5. 6.5 Programming
      1. 6.5.1 Register Write
      2. 6.5.2 Register Read
      3. 6.5.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration
        1. 6.5.3.1 Register Write With Daisy-Chain
        2. 6.5.3.2 Register Read With Daisy-Chain
  8. 7 Register Map
    1. 7.1 Register Bank 0
    2. 7.2 Register Bank 1
    3. 7.3 Register Bank 2
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Data Acquisition (DAQ) Circuit for ≤20kHz Input Signal Bandwidth
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Data Acquisition (DAQ) Circuit for ≤100kHz Input Signal Bandwidth
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Application Curves
      3. 8.2.3 Data Acquisition (DAQ) Circuit for ≤1MHz Input Signal Bandwidth
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.3.8 Data Interface

The ADS921x features a high-speed, serial LVDS data interface with 2-lane and 1-lane options for data output. The host configures the output data frame width to 20 bits or 24 bits with the single-data rate (SDR) and double-data rate (DDR) modes. Table 6-6 and Table 6-7 configuration.

Table 6-6 Register Map Settings for Output Data Interface for the ADS9217
DATA FRAME WIDTH (Bits) DATA RATE OUTPUT LANES DATA_LANES
0x12[2:0]		 DATA_RATE
0xC1[8]		 CLK1
0xC0[12]		 CLK2
0xC1[0]		 CLK3
0xC5[9]		 CLK4
0xC5[3:2]		 CLK5
0xFB[1]		 CLK6
0x1C[7:6]
20 SDR 1 5 1 1 1 1 3 0 3
20 SDR 2 0 1 0 1 0 3 0 3
20 DDR 1 5 0 1 1 1 3 0 3
20 DDR 2 0 0 0 1 0 3 0 3
24 SDR 1 7 1 1 0 1 3 0 3
24 SDR 2 2 1 0 0 0 0 0 0
24 DDR 1 7 0 1 0 1 3 0 3
24 DDR 2 2 0 0 0 0 0 0 0
Table 6-7 Register Map Settings for Output Data Interface for ADS9219 and ADS9218
DATA FRAME WIDTH (Bits) DATA RATE OUTPUT LANES DATA_LANES
0x12[2:0]		 DATA_RATE
0xC1[8]		 CLK1
0xC0[12]		 CLK2
0xC1[0]		 CLK3
0xC5[9]		 CLK4
0xC5[3:2]		 CLK5
0xFB[1]		 CLK6
0x1C[7:6]
20 SDR 1 – – – – – – – –
20 SDR 2 – – – – – – – –
20 DDR 1 – – – – – – – –
20 DDR 2 – – – – – – – –
24 SDR 1 2 1 0 0 0 0 1 0
24 SDR 2 2 1 0 0 0 0 0 0
24 DDR 1 2 0 0 0 0 0 1 0
24 DDR 2 2 0 0 0 0 0 0 0

The ADS921x generates a data clock DCLK that is a multiple of the ADC sampling clock SMPL_CLK. The data clock frequency depends on the number of data output lanes (1 or 2), data frame width, and data rate. The data frame width is 20 or 24 bits and the data rate is SDR or DDR. Equation 4 calculates the DCLK speed. Table 6-8 lists the possible values for the output data clock frequency.

Equation 4. D C L K   s p e e d =   2   A D C   c h a n n e l s   × D a t a   F r a m e   W i d t h   ( 24   b i t   o r   20   b i t ) D a t a   L a n e s   1   o r   2 × D a t a   R a t e ( S D R = 1 ,   D D R = 2 )   × S M P L _ C L K
Table 6-8 Data Clock (DCLK) Speed
ADC CHANNELS DATA FRAME WIDTH (Bits) DATA RATE
(1 = SDR, 2 = DDR)		 OUTPUT LANES(1) SMPL_CLK MULTIPLIER DCLK (SMPL_CLK = 5MHz) DCLK (SMPL_CLK = 10MHz) DCLK (SMPL_CLK = 20MHz)
2 24 1 1 48 240MHz — —
2 24 120MHz —(2) —(2)
2 1 24 120MHz 240MHz 480MHz
2 12 60MHz 120MHz 240MHz
20 1 1 40 200MHz —(3) —(3)
2 20 100MHz —(3) —(3)
2 1 20 100MHz —(3) —(3)
2 10 50MHz —(3) —(3)
(1) The LVDS output data and clock are specified up to 600MHz. Faster speeds are not supported.
(2) For the ADS9219 and ADS9218, 1-lane data output is supported only when data averaging is enabled. See the Data Averaging section.
(3) A 20-bit data frame width is not supported for the ADS9219 or ADS9218.