ADS981x アナログフロントエンド内蔵、18 ビット、2MSPS/チャネル、デュアル同時サンプリング ADC
- JAJSJW6B January 2023 – October 2024 ADS9815 , ADS9817
  
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Data Sheet

ADS981x アナログフロントエンド内蔵、18 ビット、2MSPS/チャネル、デュアル同時サンプリング ADC

このリソースの元の言語は英語です。翻訳は概要を便宜的に提供するもので、自動化ツール (機械翻訳) を使用していることがあり、TI では翻訳の正確性および妥当性につきましては一切保証いたしません。実際の設計などの前には、ti.com で必ず最新の英語版をご参照くださいますようお願いいたします。

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1 特長

8 チャネル、18 ビット、アナログフロントエンド内蔵 ADC：
- デュアル同時サンプリング：4 × 1 チャネル
- 1MΩ 固定入力インピーダンスのフロントエンド
プログラム可能なアナログ入力範囲：
- ±12V、±10V、±7V、±5V、±3.5V、±2.5V
- シングルエンドおよび差動入力
- ±12V の同相電圧範囲
- 入力過電圧保護：最大 ±18V
アナログ入力帯域幅をユーザーが選択可能：
- 21kHz と 400kHz
低ドリフトの高精度リファレンスを内蔵
- ADC リファレンス：4.096 V
- 外部回路用の 2.5V リファレンス出力
フルスループットでの非常に優れた AC および DC 性能：
- DNL：±0.5LSB、INL：±0.8LSB
- 信号対雑音比：92dB、THD：-113dB
電源：
- アナログおよびデジタル：5V および 1.8V
- デジタルインターフェイス：1.2V～1.8V
温度範囲：-40℃～+125℃

2 アプリケーション

3 概要

ADS981x は、デュアル同時サンプリング、18 ビットの逐次比較型 (SAR) A/D コンバータ (ADC) を使用した 8 チャネルのデータアクイジション (DAQ) システムです。ADS981x は、入力クランプ保護回路、1MΩ の入力インピーダンス、帯域幅をユーザーが選択可能なプログラマブルゲインアンプ (PGA) を持つ完全なアナログフロントエンドを各チャネルに備えています。入力インピーダンスが高いため、センサや変圧器と直接接続でき、外付けのドライバ回路が必要ありません。ADS981x は、最大 ±12V の入力同相電圧でユニポーラ入力またはバイポーラ入力を受け入れるように構成できます。

このデバイスは、ADC 用の 4.096V リファレンスと、外部回路で使用するための 2.5V リファレンス出力も備えています。1.2V ～ 1.8V での動作をサポートするデジタルインターフェイスにより、ADS981x は外部電圧レベル変換なしで使用できます。

パッケージ情報

部品番号	パッケージ ⁽¹⁾	パッケージサイズ⁽²⁾
ADS981x	RSH (VQFN、56)	7mm × 7mm

(1) 詳細については、「メカニカル、パッケージ、および注文情報」を参照してください。

(2) パッケージサイズ (長さ × 幅) は公称値であり、該当する場合はピンも含まれます。

製品情報

部品番号	SPEED	総電力
ADS9817	2MSPS / チャネル	232 mW
ADS9815	1MSPS / チャネル	165 mW

デバイスのブロック図

4 Pin Configuration and Functions

Figure 4-1 RSH Package,56-Pin VQFN(Top View)

Table 4-1 Pin Functions

PIN		TYPE⁽¹⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾	DESCRIPTION
AIN1M	55	AI	Analog input channel 1, negative input.
AIN1P	54	AI	Analog input channel 1, positive input.
AIN2M	2	AI	Analog input channel 2, negative input.
AIN2P	1	AI	Analog input channel 2, positive input.
AIN3M	4	AI	Analog input channel 3, negative input.
AIN3P	3	AI	Analog input channel 3, positive input.
AIN4M	6	AI	Analog input channel 4, negative input.
AIN4P	5	AI	Analog input channel 4, positive input.
AIN5M	10	AI	Analog input channel 5, negative input.
AIN5P	9	AI	Analog input channel 5, positive input.
AIN6M	12	AI	Analog input channel 6, negative input.
AIN6P	11	AI	Analog input channel 6, positive input.
AIN7M	14	AI	Analog input channel 7, negative input.
AIN7P	13	AI	Analog input channel 7, positive input.
AIN8M	17	AI	Analog input channel 8, negative input.
AIN8P	16	AI	Analog input channel 8, positive input.
AVDD_5V	15, 56	P	5V analog supply. Connect 1µF and 0.1µF decoupling capacitors to GND.
CS	25	DI	Chip-select input for SPI interface configuration; active low. This pin has an internal 100kΩ pullup resistor to IOVDD.
D0	34	DO	Serial output data lane 0.
D1	35	DO	Serial data output lane 1.
D2	36	DO	Serial data output lane 2.
D3	37	DO	Serial data output lane 3.
DCLKOUT	33	DO	Clock output for data interface.
FCLKOUT	40	DO	Frame synchronization output for data interface.
GND	7, 23, 29, 42, 46	P	Ground.
IOVDD	30, 41	P	Digital I/O supply for data interface. Connect 1µF and 0.1µF decoupling capacitor to GND.
NC	20, 38, 39, 50, 51	—	Not connected. No external connection.
PWDN	32	DI	Power-down control; active low. PWDN has an internal 100kΩ pullup resistor to the digital interface supply.
REFIO	52	AI/AO	REFIO acts as an internal reference output when the internal reference is enabled. REFIO functions as an input pin for the external reference when the internal reference is disabled. Connect a 10µF decoupling capacitor to the REFM pins.
REFM	8, 18, 53	AI	Reference ground potential. Connect to GND.
REFOUT_2V5	19	AO	2.5V reference output. Connect a decoupling 10µF capacitor to the REFM pins.
RESET	31	DI	Reset input for the device; active low. RESET has an internal 100kΩ pullup resistor to the digital interface supply.
SCLK	26	DI	Serial clock input for the configuration interface. SCLK has an internal 100kΩ pulldown resistor to the digital interface ground.
SDI	27	DI	SDI is a multifunction logic input; pin function is determined by the SPI_EN pin. SDI has an internal 100kΩ pulldown resistor to GND. SPI_EN = 0b: SDI is the logic input to select between the internal or external reference. Connect SDI to GND for the external reference. Connect SDI to IOVDD for the internal reference. SPI_EN = 1b: Serial data input for the configuration interface.
SDO	28	DO	Serial data output for the configuration interface.
SMPL_CLKP	44	DI	Single-ended ADC sampling clock input. SMPL_CLKP is the positive input for the differential sampling clock input to the ADC.
SMPL_CLKM	43	DI	Connect SMPL_CLKM to GND for a single-ended ADC sampling clock input. SMPL_CLKM is the negative input for the differential sampling clock input to the ADC.
SMPL_SYNC	45	DI	Synchronization input. See the Sample Synchronization section on how to use the SMPL_SYNC pin.
SPI_EN	24	DI	Logic input to enable the SPI interface configuration (CS, SCLK, SDI, and SDO). SPI_EN has an internal 100kΩ pullup resistor to the digital interface supply.
VDD_1V8	21, 22, 47, 48, 49	P	1.8V power-supply. Connect 1µF and 0.1µF decoupling capacitors to GND.
Thermal pad	—	P	Exposed thermal pad; connect to GND.

(1) I = input, O = output, I/O = input or output, G = ground, and P = power.

5 Specifications

5.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)⁽¹⁾

	MIN	MAX	UNIT
AVDD_5V to GND	–0.3	6	V
VDD_1V8 to GND	–0.3	2.1	V
IOVDD to GND	–0.3	2.1	V
AINxP and AINxM to GND	–18	18	V
REFIO to REFM	REFM – 0.3	AVDD_5V + 0.3	V
REFM to GND	GND – 0.3	GND + 0.3	V
Digital inputs to GND	GND – 0.3	2.1	V
Input current to any pin except supply pins⁽²⁾	–10	10	mA
Junction temperature, T_J	–40	150	°C
Storage temperature, T_stg	–60	150	°C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) Pin current must be limited to 10 mA or less.

5.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾		±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾		±500	V

(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER SUPPLY
AVDD_5V	Analog power supply	AVDD_5V to GND, 5 V	4.75	5	5.25	V
VDD_1V8	Analog power supply	VDD_1V8 to GND, 1.8 V	1.75	1.8	1.85	V
IOVDD	Digital interface power supply	IOVDD to GND	1.15	1.8	1.85	V
REFERENCE VOLTAGE
V_REF	Reference voltage to the ADC	External reference	4.092	4.096	4.100	V
ANALOG INPUTS
V_FSR	Full-scale input range	RANGE_CHx = 0010b	–2.5		2.5	V
		RANGE_CHx = 0001b	–3.5		3.5
		RANGE_CHx = 0000b	–5		5
		RANGE_CHx = 0011b	–7		7
		RANGE_CHx = 0100b	–10		10
		RANGE_CHx = 0101b	–12		12
AINxP	Operating input voltage, positive input		–17		17	V
AINxM	Operating input voltage, negative input		–17		17	V
TEMPERATURE RANGE
T_A	Ambient temperature		–40	25	125	°C

5.4 Thermal Information

THERMAL METRIC⁽¹⁾		ADS981x	UNIT
		RSH (VQFN)
		56 PINS
R_θJA	Junction-to-ambient thermal resistance	23.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	10.5	°C/W
R_θJB	Junction-to-board thermal resistance	6.1	°C/W
Ψ_JT	Junction-to-top characterization parameter	0.1	°C/W
Ψ_JB	Junction-to-board characterization parameter	6.0	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.9	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.

5.5 Electrical Characteristics

at AVDD_5V = 4.75 V to 5.25 V, VDD_1V8 = 1.75 V to 1.85 V, IOVDD = 1.15 V to 1.85 V, V_REF = 4.096 V (internal or external), wide-common-mode disabled for analog input ranges ±2.5V, ±3.5V, and ±5V, wide-common-mode enabled for analog input ranges ±7V, ±10V, and ±12V, and maximum throughput (unless otherwise noted); minimum and maximum values at T_A = –40°C to +125°C; typical values at T_A = 25°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUTS
R_IN	Input impedance	All input ranges	0.85	1	1.15	MΩ
	Input impedance thermal drift	All input ranges		10	25	ppm/°C
	Input capacitance			10		pF
ANALOG INPUT FILTER
BW_{(-3 dB)}	Analog input LPF bandwidth –3 dB	All input ranges, low-bandwidth filter		21		kHz
		RANGE = ±2.5V, wide-bandwidth filter		182
		RANGE = ±3.5V, wide-bandwidth filter		240
		RANGE = ±5V, wide-bandwidth filter		320
		RANGE = ±7V, wide-bandwidth filter		400
		RANGE = ±10V, wide-bandwidth filter		385
		RANGE = ±12V, wide-bandwidth filter		375
DC PERFORMANCE
	Resolution	No missing codes	18			Bits
DNL	Differential nonlinearity⁽³⁾	All ranges, wide-CM enabled and disabled	–0.99	±0.5	0.99	LSB
INL	Integral nonlinearity	All ranges, wide-CM enabled and disabled, T_A = 0℃ to 70℃	–4	±0.8	4	LSB
INL	Integral nonlinearity	All ranges, wide-CM enabled and disabled, T_A = –40℃ to 125℃	–4.5	±0.8	4.5	LSB
	Offset error⁽²⁾⁽⁵⁾	RANGE = ±2.5V	–175	±90	175	LSB
		RANGE = ±2.5V, wide-CM enabled		±120
		RANGE = ±3.5V	–100	±60	100
		RANGE = ±3.5V, wide-CM enabled		±80
		RANGE = ±5V	–50	±10	50
		RANGE = ±5V, wide-CM enabled		±60
		RANGE = ±7V	–100	±35	100
		RANGE = ±10V	–50	±10	50
		RANGE = ±12V	–75	±15	75
	Offset error thermal drift⁽²⁾⁽⁴⁾	All ranges, wide-CM enabled and disabled		0.5	1.5	ppm/°C
	Gain error⁽²⁾⁽⁵⁾	RANGE = ±2.5V, ±3.5V, and ±5V	–0.05	±0.02	0.05	%FSR
		RANGE = ±2.5V, ±3.5V, and ±5V, wide-CM enabled		±0.04
		RANGE = ±7V, ±10V, ±12V	–0.05	±0.02	0.05
	Gain error thermal drift⁽²⁾⁽⁴⁾	Wide-CM enabled and disabled, all ranges		0.7	3	ppm/°C
AC PERFORMANCE
SNR	Signal-to-noise ratio, low-noise filter	RANGE = ±2.5V, f_IN = 2kHz	86.7	89.5		dBFS
		RANGE = ±3.5V, f_IN = 2kHz	87.8	90.5
		RANGE = ±5V, f_IN = 2kHz	88.5	91.4
		RANGE = ±7V, f_IN = 2kHz	89.3	91.3
		RANGE = ±10V, f_IN = 2kHz	89.9	91.8
		RANGE = ±12V, f_IN = 2kHz	90	92
	Signal-to-noise ratio, wide-bandwidth filter	RANGE = ±2.5V, f_IN = 2kHz	79	82.5
		RANGE = ±3.5V, f_IN = 2kHz	80	83.5
		RANGE = ±5V, f_IN = 2kHz	80.5	84.5
		RANGE = ±7V, f_IN = 2kHz	81.5	83.5
		RANGE = ±10V, f_IN = 2kHz	83	85
		RANGE = ±12V, f_IN = 2kHz	83.5	85.5
SINAD	Signal-to-noise + distortion ratio, low-noise filter	RANGE = ±2.5V, f_IN = 2kHz	85.7	88.9		dB
		RANGE = ±3.5V, f_IN = 2kHz	86.7	89.9
		RANGE = ±5V, f_IN = 2kHz	87.3	90.7
		RANGE = ±7V, f_IN = 2kHz	88.0	90.6
		RANGE = ±10V, f_IN = 2kHz	88.5	91.1
		RANGE = ±12V, f_IN = 2kHz	88.6	91.3
	Signal-to-noise + distortion ratio, wide-bandwidth filter	RANGE = ±2.5V, f_IN = 2kHz	78.6	82.2
		RANGE = ±3.5V, f_IN = 2kHz	79.5	83.2
		RANGE = ±5V, f_IN = 2kHz	80.0	84.2
		RANGE = ±7V, f_IN = 2kHz	80.9	83.2
		RANGE = ±10V, f_IN = 2kHz	82.3	84.7
		RANGE = ±12V, f_IN = 2kHz	82.8	85.1
THD	Total harmonic distortion	All ranges, low-noise filter, f_IN = 2kHz		–113		dB
THD	Total harmonic distortion	All ranges, wide-bandwidth filter, f_IN = 2kHz		–113		dB
SFDR	Spurious-free dynamic range	All ranges, f_IN = 2kHz		113		dB
	CMRR	at dc		–70		dB
	Isolation crosstalk	at dc		–100		dB
INTERNAL REFERENCE
V_REF⁽¹⁾	Voltage on REFIO pin (configured as output)	1µF capacitor on REFIO pin, T_A = 25°C	4.092	4.096	4.1	V
	Reference temperature drift⁽⁴⁾			10	25	ppm/°C
DIGITAL INPUTS
V_IL	Input low logic level		–0.3		0.3 IOVDD	V
V_IH	Input high logic level		0.7 IOVDD		IOVDD	V
	Input current			0.1		µA
	Input capacitance			6		pF
LVDS SAMPLING CLOCK INPUT
V_TH	High-level input voltage	AC coupled	100			mV
V_TH	High-level input voltage	DC coupled	300			mV
V_TL	Low-level input voltage	AC coupled			–100	mV
V_TL	Low-level input voltage	DC coupled			–300	mV
V_ICM	Input common-mode voltage		0.3	1.2	1.4	V
DIGITAL OUTPUTS
V_OL	Output low logic level	I_OL = 500µA sink	0		0.2 IOVDD	V
V_OH	Output high logic level	I_OH = 500µA source	0.8 IOVDD		IOVDD	V
POWER SUPPLY - ADS9817
	Total power dissipation	Maximum throughput		232	304	mW
I_{AVDD_5V}	Supply current from AVDD_5V	Maximum throughput, internal reference		26	32	mA
I_{AVDD_5V}	Supply current from AVDD_5V	Power-down		0.2	2	mA
I_{VDD_1V8}	Supply current from VDD_1V8	Maximum throughput, internal reference		50	70	mA
I_{VDD_1V8}	Supply current from VDD_1V8	Power-down		0.2	8	mA
I_IOVDD	Supply current from IOVDD	Maximum throughput		7	10	mA
I_IOVDD	Supply current from IOVDD	Power-down		0.1	3	mA
POWER SUPPLY - ADS9815
	Total power dissipation	Maximum throughput		165	215	mW
I_{AVDD_5V}	Supply current from AVDD_5V	Maximum throughput, internal reference		19	25	mA
I_{AVDD_5V}	Supply current from AVDD_5V	Power-down		0.2	2	mA
I_{VDD_1V8}	Supply current from VDD_1V8	Maximum throughput, internal reference		35	43	mA
I_{VDD_1V8}	Supply current from VDD_1V8	Power-down		0.2	8	mA
I_IOVDD	Supply current from IOVDD	Maximum throughput		4	7	mA
I_IOVDD	Supply current from IOVDD	Power-down		0.1	3	mA

(1) Does not include the variation in voltage resulting from solder shift effects.

(2) These specifications include full temperature range variation but not the error contribution from internal reference. Measured with single-ended inputs as described in Wide Common-Mode Configuration for Single-Ended Inputs

(3) Wide-CM refers to wide-common-mode voltage at the analog inputs. See section on Section 6.3.1.3 for more details.

(4) Thermal drift is the difference between maximum and minimum error measured over the temperature range, divided by the temperature range.

(5) Minimum and maximum specifications are applicable for low-bandwidth filter setting.

5.6 Timing Requirements

at AVDD_5V = 4.75 V to 5.25 V, VDD_1V8 = 1.75 V to 1.85 V, IOVDD = 1.15 V to 1.85 V, and maximum throughput (unless otherwise noted); minimum and maximum values at T_A = -40°C to +125°C; typical values at T_A = 25°C

			MIN	MAX	UNIT
CONVERSION CYCLE
f_{SMPL_CLK}	Sampling frequency	ADS9817	3.9	8.1	MHz
f_{SMPL_CLK}	Sampling frequency	ADS9815	3.9	4.1	MHz
t_{SMPL_CLK}	Sampling time interval		1 / f_{SMPL_CLK}		ns
t_{PL_SMPL_CLK}	SMPL_CLK low time		0.45 t_{SMPL_CLK}	0.55 t_{SMPL_CLK}	ns
t_{PH_SMPL_CLK}	SMPL_CLK high time		0.45 t_{SMPL_CLK}	0.55 t_{SMPL_CLK}	ns
SPI INTERFACE TIMINGS (CONFIGURATION INTERFACE)
f_SCLK	Maximum SCLK frequency			20	MHz
t_{PH_CK}	SCLK high time		0.48	0.52	t_CLK
t_{PL_CK}	SCLK low time		0.48	0.52	t_CLK
t_{hi_CS}	Pulse duration: CS high		220		ns
t_{d_CSCK}	Delay time: CS falling to the first SCLK capture edge		20		ns
t_{su_CKDI}	Setup time: SDI data valid to the SCLK rising edge		10		ns
t_{ht_CKDI}	Hold time: SCLK rising edge to data valid on SDI		5		ns
t_{D_CKCS}	Delay time: last SCLK falling to CS rising		5		ns
CMOS DATA INTERFACE
t_{su_SS}	Setup time: SMPL_SYNC rising edge to SMPL_CLK falling edge		10		ns
t_{ht_SS}	Hold time: SMPL_CLK falling edge to SMPL_SYNC high		10		ns

5.7 Switching Characteristics

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
RESET
t_PU	Power-up time for device			25	ms
SPI INTERFACE TIMINGS (CONFIGURATION INTERFACE)
t_{den_CKDO}	Delay time: 8^th SCLK rising edge to data enable			22	ns
t_{dz_CKDO}	Delay time: 24^th SCLK rising edge to SDO going Hi-Z			50	ns
t_{d_CKDO}	Delay time: SCLK falling edge to corresponding data valid on SDO			16	ns
t_{ht_CKDO}	Delay time: SCLK falling edge to previous data valid on SDO		2		ns
CMOS DATA INTERFACE
t_DCLK	Data clock output	DDR mode	10		ns
t_DCLK	Data clock output	SDR mode	20		ns
	Clock duty cycle		45	55	%
t_{off_DCLKDO_r}	Time offset: DCLK rising to corresponding data valid	DDR mode	t_DCLK/ 4 – 1.5	t_DCLK/ 4 + 1.5	ns
t_{off_DCLKDO_f}	Time offset: DCLK falling to corresponding data valid	DDR mode	t_DCLK/ 4 – 1.5	t_DCLK/ 4 + 1.5	ns
t_{d_DCLKDO}	Time delay: DCLK rising to corresponding data valid	SDR mode	–1	1	ns
t_{d_SYNC_FCLK}	Time delay: SMPL_CLK falling edge with SYNC signal to corresponding FCLKOUT rising edge		3	4	t_{SMPL_CLK}

5.8 Timing Diagrams

ADS9815 ADS9817 SPI Configuration
Interface

Figure 5-1 SPI Configuration Interface

ADS9815 ADS9817 4-SDO DDR CMOS Data
Interface

Figure 5-2 4-SDO DDR CMOS Data Interface

ADS9815 ADS9817 2-SDO DDR CMOS Data
Interface

Figure 5-3 2-SDO DDR CMOS Data Interface

ADS9815 ADS9817 4-SDO SDR CMOS Data
Interface

Figure 5-4 4-SDO SDR CMOS Data Interface

ADS9815 ADS9817 2-SDO SDR CMOS Data
Interface

Figure 5-5 2-SDO SDR CMOS Data Interface

5.9 Typical Characteristics

ADS9815 ADS9817 Typical
INL With Low-Bandwidth LPF

Figure 5-6 Typical INL With Low-Bandwidth LPF

ADS9815 ADS9817 Typical
DNL With Low-Noise LPF

Figure 5-8 Typical DNL With Low-Noise LPF

ADS9815 ADS9817 Typical
FFT With Low-Bandwidth LPF, RANGE =
±5V

SNR = 91.5dBFS, THD = –113dB at f_IN = 2kHz

Figure 5-10 Typical FFT With Low-Bandwidth LPF,
RANGE = ±5V

ADS9815 ADS9817 Typical
FFT With Low-Bandwidth LPF, RANGE =
±10V

SNR = 92.1dBFS, THD = –113dB at f_IN = 2kHz

Figure 5-12 Typical FFT With Low-Bandwidth LPF,
RANGE = ±10V

ADS9815 ADS9817 Low-Bandwidth
LPF Frequency Response Across Input Ranges

Typical bandwidth (–3dB) = 21.2kHz

Figure 5-14 Low-Bandwidth LPF Frequency Response Across Input Ranges

ADS9815 ADS9817 SNR vs Input Signal
Frequency Across Input Ranges With Low-Bandwidth LPF

Figure 5-16 SNR vs Input Signal Frequency Across Input Ranges With Low-Bandwidth LPF

ADS9815 ADS9817 THD vs Input Signal
Frequency Across Input Ranges With Low-Bandwidth LPF

Figure 5-18 THD vs Input Signal Frequency Across Input Ranges With Low-Bandwidth LPF

ADS9815 ADS9817 SINAD vs Input Signal
Frequency Across Input Ranges With Low-Bandwidth LPF

Figure 5-20 SINAD vs Input Signal Frequency Across Input Ranges With Low-Bandwidth LPF

ADS9815 ADS9817 THD vs Input Frequency,
Low-BW Mode, RANGE = ±5V, ADS9817

Figure 5-22 THD vs Input Frequency, Low-BW Mode,
RANGE = ±5V, ADS9817

ADS9815 ADS9817 THD vs Input Frequency,
Low-BW Mode, RANGE = ±10V, ADS9817

Figure 5-24 THD vs Input Frequency, Low-BW Mode,
RANGE = ±10V, ADS9817

ADS9815 ADS9817 THD vs Input Frequency,
Low-BW Mode, RANGE = ±5V, ADS9815

Figure 5-26 THD vs Input Frequency, Low-BW Mode,
RANGE = ±5V, ADS9815

ADS9815 ADS9817 THD vs Input Frequency,
Low-BW Mode, RANGE = ±10V, ADS9815

Figure 5-28 THD vs Input Frequency, Low-BW Mode,
RANGE = ±10V, ADS9815

ADS9815 ADS9817 THD vs Input Amplitude,
RANGE = ±5V

Figure 5-30 THD vs Input Amplitude, RANGE = ±5V

Figure 5-32 INL vs Temperature

ADS9815 ADS9817 Offset Error vs
Temperature, RANGE = ±5V

Figure 5-34 Offset Error vs Temperature, RANGE = ±5V

ADS9815 ADS9817 Offset Error Drift
Histogram

Figure 5-36 Offset Error Drift Histogram

ADS9815 ADS9817 Gain Error vs Temperature,
RANGE = ±10V

Figure 5-38 Gain Error vs Temperature, RANGE = ±10V

ADS9815 ADS9817 DC Histogram of Codes for
AINxP = AINxM = GND, Low-BW Mode, RANGE = ±5V

Mean = 131073.8LSB, standard deviation = 2.45LSB, number of hits = 4096

Figure 5-40 DC Histogram of Codes for AINxP = AINxM = GND, Low-BW Mode, RANGE = ±5V

ADS9815 ADS9817 DC Histogram of Codes for
AINxP = AINxM = GND, Wide-BW Mode, RANGE = ±5V

Mean = 131074.4LSB, standard deviation = 5.47LSB, number of hits = 4096

Figure 5-42 DC Histogram of Codes for AINxP = AINxM = GND, Wide-BW Mode, RANGE = ±5V

Figure 5-44 REFIO vs Temperature

ADS9815 ADS9817 Supply Currents and Total
Power Dissipation vs Temperature

Figure 5-46 Supply Currents and Total Power Dissipation vs Temperature

ADS9815 ADS9817 Typical
INL With Wide-Bandwidth LPF

Figure 5-7 Typical INL With Wide-Bandwidth LPF

ADS9815 ADS9817 Typical
DNL With Wide-Bandwidth LPF

Figure 5-9 Typical DNL With Wide-Bandwidth LPF

ADS9815 ADS9817 Typical
FFT With Wide-Bandwidth LPF, RANGE =
±5V

SNR = 84.5dBFS, THD = –113dB at f_IN = 2kHz

Figure 5-11 Typical FFT With Wide-Bandwidth LPF,
RANGE = ±5V

ADS9815 ADS9817 Typical
FFT With Wide-Bandwidth LPF, RANGE =
±10V

SNR = 85.5dBFS, THD = –113dB at f_IN = 2kHz

Figure 5-13 Typical FFT With Wide-Bandwidth LPF,
RANGE = ±10V

ADS9815 ADS9817 Wide-Bandwidth
LPF Frequency Response Across Input Ranges

Figure 5-15 Wide-Bandwidth LPF Frequency Response Across Input Ranges

ADS9815 ADS9817 SNR vs Input Signal
Frequency Across Input Ranges With Wide-Bandwidth LPF

Figure 5-17 SNR vs Input Signal Frequency Across Input Ranges With Wide-Bandwidth LPF

ADS9815 ADS9817 THD vs Input Signal
Frequency Across Input Ranges With Wide-Bandwidth LPF

Figure 5-19 THD vs Input Signal Frequency Across Input Ranges With Wide-Bandwidth LPF

ADS9815 ADS9817 SINAD vs Input Signal
Frequency Across Input Ranges With Wide-Bandwidth LPF

Figure 5-21 SINAD vs Input Signal Frequency Across Input Ranges With Wide-Bandwidth LPF

ADS9815 ADS9817 THD vs Input Frequency,
High-BW Mode, RANGE = ±5V, ADS9817

Figure 5-23 THD vs Input Frequency, High-BW Mode,
RANGE = ±5V, ADS9817

ADS9815 ADS9817 THD vs Input Frequency,
High-BW Mode, RANGE = ±10V, ADS9817

Figure 5-25 THD vs Input Frequency, High-BW Mode,
RANGE = ±10V, ADS9817

ADS9815 ADS9817 THD vs Input Frequency,
High-BW Mode, RANGE = ±5V, ADS9815

Figure 5-27 THD vs Input Frequency, High-BW Mode,
RANGE = ±5V, ADS9815

ADS9815 ADS9817 THD vs Input Frequency,
High-BW Mode, RANGE = ±10V, ADS9815

Figure 5-29 THD vs Input Frequency, High-BW Mode,
RANGE = ±10V, ADS9815

ADS9815 ADS9817 THD vs Input Amplitude,
RANGE = ±10V

Figure 5-31 THD vs Input Amplitude, RANGE = ±10V

Figure 5-33 DNL vs Temperature

ADS9815 ADS9817 Offset Error vs
Temperature, RANGE = ±10V

Figure 5-35 Offset Error vs Temperature, RANGE = ±10V

ADS9815 ADS9817 Gain Error vs Temperature,
RANGE = ±5V

Figure 5-37 Gain Error vs Temperature, RANGE = ±5V

ADS9815 ADS9817 Gain Error Drift
Histogram

Figure 5-39 Gain Error Drift Histogram

ADS9815 ADS9817 DC Histogram of Codes for
VIN = 1mV, Low-BW Mode, RANGE = ±5V

Mean = 131103.5LSB, standard deviation = 2.49LSB, number of hits = 4096

Figure 5-41 DC Histogram of Codes for V_IN = 1mV, Low-BW Mode, RANGE = ±5V

ADS9815 ADS9817 DC Histogram of Codes for
VIN = 1mV, Wide-BW Mode, RANGE = ±5V

Mean = 131102.3LSB, standard deviation = 5.68LSB, number of hits = 4096

Figure 5-43 DC Histogram of Codes for V_IN = 1mV, Wide-BW Mode, RANGE = ±5V

ADS9815 ADS9817 REFOUT_2V5 vs
Temperature

Figure 5-45 REFOUT_2V5 vs Temperature

6 Detailed Description

6.1 Overview

The ADS981x is an 18-bit data acquisition (DAQ) system with eight-channel analog inputs that can be configured as either single-ended or differential. Each analog input channel consists of an input clamp protection circuit, and a programmable gain amplifier (PGA) with user-selectable bandwidth options. The input signals are digitized using an 18-bit analog-to-digital converter (ADC), based on the successive approximation register (SAR) architecture. This overall system can achieve a maximum throughput of 2 MSPS/channel for all channels. The device features a 4.096V internal reference with a fast-settling buffer.

The device operates from 5V and 1.8V analog supplies and can accommodate true bipolar input signals. The input clamp protection circuitry can tolerate voltages up to ±18V. The device offers a constant 1MΩ resistive input impedance irrespective of the sampling frequency or the selected input range. The ADS981x offers a simplified end solution without requiring external high-voltage bipolar supplies and complicated driver circuits.