JAJSJW6B January 2023 – October 2024 ADS9815 , ADS9817
PRODUCTION DATA
The ADS981x supports 2-lane and 4-lane mode with single-data-rate (SDR) and double-data-rate (DDR) interface modes. The data interface can be selected using the configuration SPI as described in Table 6-7. The ADC generates the data (D[3:0]), data clock (DCLKOUT), and frame clock (FCLKOUT) in response to the sampling clock signal on the SMPL_CLK input pin. The 18-bit ADC conversion result is output MSB first in a 24-bit data packet and the last six bits are zeroes.
The data interface signals can be described as:
Use the registers in Table 6-7 to configure the data interface.
INTERFACE MODE | FIGURE | DATA_RATE (Address = 0xC1) |
DATA_LANES (Address = 0xC1) |
---|---|---|---|
4-lane, DDR | Figure 5-2 | 0 | 0 |
2-lane, DDR | Figure 5-3 | 0 | 1 |
4-lane, SDR | Figure 5-4 | 1 | 0 |
2-lane, SDR | Figure 5-5 | 1 | 1 |