JAJSJW6B January   2023  – October 2024 ADS9815 , ADS9817

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
        1. 6.3.1.1 Input Clamp Protection Circuit
        2. 6.3.1.2 Programmable Gain Amplifier (PGA)
        3. 6.3.1.3 Wide-Common-Mode Voltage Rejection Circuit
        4. 6.3.1.4 Gain Error Calibration
      2. 6.3.2 ADC Transfer Function
      3. 6.3.3 ADC Sampling Clock Input
      4. 6.3.4 Reference
        1. 6.3.4.1 Internal Reference Voltage
        2. 6.3.4.2 External Reference Voltage
      5. 6.3.5 Sample Synchronization
      6. 6.3.6 Data Interface
        1. 6.3.6.1 Data Clock Output
        2. 6.3.6.2 ADC Output Data Randomizer
        3. 6.3.6.3 Test Patterns for Data Interface
          1. 6.3.6.3.1 Fixed Pattern
          2. 6.3.6.3.2 Digital Ramp
          3. 6.3.6.3.3 Alternating Test Pattern
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power-Down
      2. 6.4.2 Reset
      3. 6.4.3 Initialization Sequence
      4. 6.4.4 Normal Operation
    5. 6.5 Programming
      1. 6.5.1 Register Write
      2. 6.5.2 Register Read
      3. 6.5.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration
        1. 6.5.3.1 Register Write With Daisy-Chain
        2. 6.5.3.2 Register Read With Daisy-Chain
  8. 7 Register Map
    1. 7.1 Register Bank 0
    2. 7.2 Register Bank 1
    3. 7.3 Register Bank 2
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Parametric Measurement Unit (PMU)
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.3.1.3 Wide-Common-Mode Voltage Rejection Circuit

The ADS981x features a common-mode (CM) rejection circuit at the analog inputs that supports CM voltages up to ±12V. The CM voltage for differential inputs is given by Equation 1. On power-up or after reset, the common-mode voltage range for the analog input channels is ±12V (CM_CTRL_EN = 0b). Voltage at the analog inputs, in all cases, must be within the Absolute Maximum Ratings.

Equation 1. C o m m o n   m o d e   v o l t a g e =   ( Voltage on AINP ) + ( Voltage on AINM ) 2

As described in Table 6-3, the CM voltage rejection circuit can be optimized for various CM voltages for differential inputs.

Table 6-3 Wide Common-Mode Configuration for Differential Inputs
COMMON-MODE (CM) RANGE CM_CTRL_EN ADC A
(ANALOG INPUT CHANNELS 1–4)		 ADC B
(ANALOG INPUT CHANNELS 5–8)
CM_EN_CH[4:1] CM_RNG_CH[4:1] CM_EN_CH[8:5] CM_RNG_CH[8:5]
CM ≤ ±1V 1 0 Don't care 0 Don't care
CM ≤ ±RANGE / 2 1 0 1 0
CM ≤ ±6V 1 1
CM ≤ ±12V 2 2

The CM voltage rejection circuit must be configured depending on the analog input range of the PGA when using single-ended inputs as well. Table 6-4 lists the recommended configuration for single-ended inputs for various analog input voltage ranges.

Table 6-4 Wide Common-Mode Configuration for Single-Ended Inputs
PGA ANALOG INPUT RANGE CM_CTRL_EN ADC A
(ANALOG INPUT CHANNELS 1–4)		 ADC B
(ANALOG INPUT CHANNELS 5–8)
CM_EN_CH[4:1] CM_RNG_CH[4:1] CM_EN_CH[8:5] CM_RNG_CH[8:5]
±2.5V, ±3.5V, and ±5V 1 0 Don't care 0 Don't care
±7V, ±10V, and ±12V 1 0 1 0