JAJSHJ6B December   2011  – June 2019 AFE030

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック図
  4. 4 改訂履歴
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Thermal Information
    4. 7.4  Electrical Characteristics: Transmitter (Tx), Tx_DAC
    5. 7.5  Electrical Characteristics: Transmitter (Tx), Tx_PGA
    6. 7.6  Electrical Characteristics: Transmitter (Tx), Tx_FILTER
    7. 7.7  Electrical Characteristics: Power Amplifier (PA)
    8. 7.8  Electrical Characteristics: Receiver (Rx), Rx PGA1
    9. 7.9  Electrical Characteristics: Receiver (Rx), Rx Filter
    10. 7.10 Electrical Characteristics: Receiver (Rx), Rx PGA2
    11. 7.11 Electrical Characteristics: Digital
    12. 7.12 Electrical Characteristics: Two-Wire Interface
    13. 7.13 Electrical Characteristics: Zero-Crossing Detector
    14. 7.14 Electrical Characteristics: Internal Bias Generator
    15. 7.15 Electrical Characteristics: Power Supply
    16. 7.16 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Requirements
    2. 8.2 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 PA Block
      2. 9.3.2 Tx Block
      3. 9.3.3 Rx Block
      4. 9.3.4 DAC Block
      5. 9.3.5 REF1 and REF2 Blocks
      6. 9.3.6 Zero Crossing Detector Block
      7. 9.3.7 ETx and ERx Blocks
    4. 9.4 Power Supplies
    5. 9.5 Pin Descriptions
      1. 9.5.1 Current Overload
      2. 9.5.2 Thermal Overload
    6. 9.6 Calibration Modes
      1. 9.6.1 Tx Calibration Mode
      2. 9.6.2 Rx Calibration Mode
    7. 9.7 Serial Interface
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
    3. 10.3 Line-Coupling Circuit
    4. 10.4 Circuit Protection
    5. 10.5 Thermal Considerations
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 TINA-TI™ (無料のダウンロード・ソフトウェア)
        2. 11.1.1.2 TI Precision Designs
        3. 11.1.1.3 WEBENCH Filter Designer
      2. 11.1.2 電力線通信開発者用キット
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 Electrical Characteristics: Transmitter (Tx), Tx_FILTER

At TJ = 25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
Input voltage range GND – 0.1 AVDD + 0.1 V
RI Input resistance
(Tx_F_IN1 and Tx_F_IN2)		 43 kΩ
FREQUENCY RESPONSE
CENELEC A Mode
Passband frequency –3 dB 95 kHz
Stop band attenuation –50 –60 dB
Stop band frequency 910 kHz
Filter gain 0 dB
CENELEC B/C/D MODES
Passband frequency –3 dB 145 kHz
Stop band attenuation –50 –60 dB
Stop band frequency 870 kHz
Filter gain 0 dB
OUTPUT
VO Voltage output swing from
AGND or AVDD 		RLOAD = 10 kΩ,
connected to AVDD/2		 10 100 mV
IO Maximum continuous current, dc Sourcing 25 mA
Sinking 25 mA
RO Output resistance f = 100 kHz 1 Ω
TRANSMITTER NOISE
Integrated noise at
PA output(1) 		CENELEC Band A
(40 kHz to 90 kHz)		 Noise-reducing capacitor = 1 nF from pin 19 to ground 435 μVRMS
CENELEC Bands B/C/D
(95 kHz to 140 kHz)		 Noise-reducing capacitor = 1 nF from pin 19 to ground 460 μVRMS
(1) Includes DAC, Tx_PGA, Tx_Filter, PA, and REF1 bias generator.