JAJSHJ6B December   2011  – June 2019 AFE030

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック図
  4. 4 改訂履歴
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Thermal Information
    4. 7.4  Electrical Characteristics: Transmitter (Tx), Tx_DAC
    5. 7.5  Electrical Characteristics: Transmitter (Tx), Tx_PGA
    6. 7.6  Electrical Characteristics: Transmitter (Tx), Tx_FILTER
    7. 7.7  Electrical Characteristics: Power Amplifier (PA)
    8. 7.8  Electrical Characteristics: Receiver (Rx), Rx PGA1
    9. 7.9  Electrical Characteristics: Receiver (Rx), Rx Filter
    10. 7.10 Electrical Characteristics: Receiver (Rx), Rx PGA2
    11. 7.11 Electrical Characteristics: Digital
    12. 7.12 Electrical Characteristics: Two-Wire Interface
    13. 7.13 Electrical Characteristics: Zero-Crossing Detector
    14. 7.14 Electrical Characteristics: Internal Bias Generator
    15. 7.15 Electrical Characteristics: Power Supply
    16. 7.16 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Requirements
    2. 8.2 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 PA Block
      2. 9.3.2 Tx Block
      3. 9.3.3 Rx Block
      4. 9.3.4 DAC Block
      5. 9.3.5 REF1 and REF2 Blocks
      6. 9.3.6 Zero Crossing Detector Block
      7. 9.3.7 ETx and ERx Blocks
    4. 9.4 Power Supplies
    5. 9.5 Pin Descriptions
      1. 9.5.1 Current Overload
      2. 9.5.2 Thermal Overload
    6. 9.6 Calibration Modes
      1. 9.6.1 Tx Calibration Mode
      2. 9.6.2 Rx Calibration Mode
    7. 9.7 Serial Interface
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
    3. 10.3 Line-Coupling Circuit
    4. 10.4 Circuit Protection
    5. 10.5 Thermal Considerations
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 TINA-TI™ (無料のダウンロード・ソフトウェア)
        2. 11.1.1.2 TI Precision Designs
        3. 11.1.1.3 WEBENCH Filter Designer
      2. 11.1.2 電力線通信開発者用キット
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.1 PA Block

Figure 24 shows a typical powerline communications application system diagram. Table 2 is a complete list of the sections within the AFE030.

AFE030 ai_sys_fbd_bos588.gifFigure 24. Typical Powerline Communications System Diagram

Table 2. Block Descriptions

BLOCK DESCRIPTION
PA The PA block includes the power amplifier and associated pedestal biasing circuitry
Tx The Tx block includes the Tx_Filter and the Tx_PGA
Rx The Rx block includes the Rx PGA1, the Rx Filter, and the Rx PGA2
ERx The ER block includes the two-wire receiver
ETx The ER block includes the two-wire transmitter
DAC The DAC block includes a digital-to-analog converter
ZC The ZC block includes both zero crossing detectors
REF1 The REF1 block includes the internal bias generator for the PA block
REF2 The REF2 block includes the internal bias generators for the Tx, Rx, ERx, and ETx blocks

The power amplifier (PA) block consists of a high slew rate, high-voltage, and high-current operational amplifier. The PA is configured with an inverting gain of 6.5 V/V, has a low-pass filter response, and maintains excellent linearity and low distortion. The PA is specified to operate from 7 V to 26 V and can deliver up to ±1 A of continuous output current over the specified junction temperature range of –40°C to +125°C. Figure 25 illustrates the PA block.

AFE030 ai_pa_fbd_generic_bos588.gifFigure 25. PA Block Equivalent Circuit

Connecting the PA in a typical PLC application requires only two additional components: an ac coupling capacitor, CIN, and the current limit programming resistor, RSET. Figure 26 shows the typical connections to the PA block.

AFE030 ai_pa_fbd_config_bos588.gifFigure 26. Typical Connections to the PA

The external capacitor, CIN, introduces a single-pole, high-pass characteristic to the PA transfer function; combined with the inherent low-pass transfer function, this characteristic results in a passband response. The value of the high-pass cutoff frequency is determined by CIN reacting with the input resistance of the PA circuit, and can be found from Equation 1:

Equation 1. AFE030 q_cin01_bos588.gif

Where:

  • CIN = external input capacitor
  • fHP = desired high-pass cutoff frequency

For example, setting CIN to 3.3 nF results in a high-pass cutoff frequency of 2.4 kHz. The voltage rating for CIN should be determined to withstand operation up to the PA power-supply voltage.

When the transmitter is not in use, the output can be disabled and placed into a high-impedance state by writing a '0' to the PA-OUT bit in the Enable2 Register. Additional power savings can be realized by shutting down the PA when not in use. Shutting down the PA for power savings is accomplished by writing a '0' to the PA bit in the Enable1 Register. Shutting down the PA also results in the PA output entering a high-impedance state. When the PA shuts down, it consumes only 2 mW of power.

The PA_ISET pin (pin 46) provides a resistor-programmable output current limit for the PA block. Equation 2 determines the value of the external RSET resistor attached to this pin.

Equation 2. AFE030 q_rset_bos588.gif

Where:

  • RSET = the value of the external resistor connected between pin 46 and ground.
  • ILIM = the value of the desired current limit for the PA.

Note that to ensure proper design margin with respect to manufacturing and temperature variations, a 30% increase in the value used in Equation 2 for ILIM over the nominal value of ILIM is recommended. See Figure 16, PA Current Limit vs RSET. For maximum output current, PA_ISET (pin 46) may be connected directly to ground.