JAJSRL6 November 2023 AFE432A3W , AFE532A3W
PRODUCTION DATA
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADC-DATA | X | ADC-DRDY | |||||||||||||
R/W-000h | X-0h | R-1h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-4 | ADC-DATA[9:0] | R/W | 000h | ADC data. Data are in straight-binary format. MSB left-aligned. Use the following bit-alignment for readback: {ADC-DATA[9:0], X, X}X = Don't care bits. |
3-1 | X | X | 0h | Don't care |
0 | ADC-DRDY | R | 1h | 0: Default state after ADC is triggered.
ADC data is invalid. 1: Default state when ADC is not triggered. The value 1 indicates ADC data is valid after the ADC is triggered. |