JAJSLP2A august   2021  – july 2023 AFE439A2 , AFE539A4 , AFE639D2

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  熱に関する情報
    5. 6.5  Electrical Characteristics: Voltage Output
    6. 6.6  Electrical Characteristics: Comparator Mode
    7. 6.7  Electrical Characteristics: ADC Input
    8. 6.8  Electrical Characteristics: General
    9. 6.9  Timing Requirements: I2C Standard Mode
    10. 6.10 Timing Requirements: I2C Fast Mode
    11. 6.11 Timing Requirements: I2C Fast Mode Plus
    12. 6.12 Timing Requirements: SPI Write Operation
    13. 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    14. 6.14 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    15. 6.15 Timing Requirements: PWM Output
    16. 6.16 Timing Requirements: I2C Controller
    17. 6.17 Timing Diagrams
    18. 6.18 Typical Characteristics: Voltage Output
    19. 6.19 Typical Characteristics: ADC
    20. 6.20 Typical Characteristics: Comparator
    21. 6.21 Typical Characteristics: General
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Smart Analog Front End (AFE) Architecture
      2. 7.3.2 Programming Interface
      3. 7.3.3 Nonvolatile Memory (NVM)
        1. 7.3.3.1 NVM Cyclic Redundancy Check (CRC)
          1. 7.3.3.1.1 NVM-CRC-FAIL-USER Bit
          2. 7.3.3.1.2 NVM-CRC-FAIL-INT Bit
      4. 7.3.4 Power-On Reset (POR)
      5. 7.3.5 External Reset
      6. 7.3.6 Register-Map Lock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Voltage-Output Mode
      2. 7.4.2 Voltage Reference and DAC Transfer Function
        1. 7.4.2.1 Power-Supply as Reference
        2. 7.4.2.2 Internal Reference
        3. 7.4.2.3 External Reference
      3. 7.4.3 Comparator Mode
      4. 7.4.4 Analog-to-Digital Converter (ADC) Mode
      5. 7.4.5 Pulse-Width Modulation (PWM)
      6. 7.4.6 Proportional-Integral (PI) Control
        1. 7.4.6.1 AFE439A2 PI Control
        2. 7.4.6.2 AFE539A4 PI Control
        3. 7.4.6.3 AFE639D2 PI Control
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
    6. 7.6 Register Maps
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-x-VOUT-CMP-CONFIG Register (address = 03h, 09h, 0Fh, 15h)
      3. 7.6.3  COMMON-CONFIG Register (address = 1Fh)
      4. 7.6.4  COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      5. 7.6.5  COMMON-PWM-TRIG Register (address = 21h) [reset = 0000h]
      6. 7.6.6  GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      7. 7.6.7  INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      8. 7.6.8  STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0003h]
      9. 7.6.9  STATE-MACHINE-CONFIG1 Register (address = 29h) [reset = C800h]
      10. 7.6.10 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      11. 7.6.11 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4.5 Pulse-Width Modulation (PWM)

The AFE439A2 provides a 7-bit duty-cycle PWM output on the SDA/SCLK/PWM pin. Pull the VREF/MODE pin high to enable PWM functionality. Table 7-3 lists all the possible PWM frequency configurations.

Table 7-3 PWM Frequency Configuration
SRAM REGISTER PWM-FREQUENCY PWM FREQUENCY (kHz) DUTY CYCLE (%) FOR CODE 1 DUTY CYCLE (%) FOR CODE 126
PWM-FREQUENCY (0x21[4:0])(1) 0 Invalid N/A N/A
1 48.828 4.88 95.12
2 24.414 2.44 97.56
3 16.276 1.63 98.37
4 12.207 1.22 98.44
5 8.138 0.81 98.44
6 6.104 0.78 98.44
7 3.052 0.78 98.44
8 2.035 0.78 98.44
9 1.526 0.78 98.44
10 1.221 0.78 98.44
11 1.017 0.78 98.44
12 0.872 0.78 98.44
13 0.763 0.78 98.44
14 0.678 0.78 98.44
15 0.610 0.78 98.44
16 0.555 0.78 98.44
17 0.509 0.78 98.44
18 0.470 0.78 98.44
19 0.436 0.78 98.44
20 0.407 0.78 98.44
21 0.381 0.78 98.44
22 0.359 0.78 98.44
23 0.339 0.78 98.44
24 0.321 0.78 98.44
25 0.305 0.78 98.44
26 0.291 0.78 98.44
27 0.277 0.78 98.44
28 0.265 0.78 98.44
29 0.254 0.78 98.44
30 0.244 0.78 98.44
31 0.218 0.78 98.44
(1) The PWM-FREQUENCY shares SRAM location with MIN-OUTPUT (0x21[15:9]). Therefore, both these parameters must be written together.

The duty cycle of the PWM is proportional to the 7-bit code, 0d to 126d. As Table 7-4 shows, the code 127d corresponds to 100% duty cycle. The duty cycle 99.22% (127d/128d) is skipped to achieve 100% duty cycle using a 7-bit code. The PWM duty-cycle setting is done by the state machine and is not exposed to the user.

Table 7-4 PWM Duty Cycle Setting
CODE DUTY-CYCLE DESCRIPTION
0 0% Always 0
1 0.78% Minimum linear duty cycle
x (x/128)% x is the code between 2d and 125d, both included.
126 98.44% Maximum linear duty cycle
127 100% Always 1. The duty cycle 99.22% (127d/128d) is skipped.