8.3.1.1 Receiver Front-End

The receiver consists of a differential current-to-voltage (I-V) transimpedance amplifier that converts the input photodiode current into an appropriate voltage, as shown in Figure 55. The feedback resistor of the amplifier (R_F) is programmable to support a wide range of photodiode currents. Available R_F values include: 1 MΩ, 500 kΩ,
250 kΩ, 100 kΩ, 50 kΩ, 25 kΩ, and 10 kΩ.

Figure 55. Receiver Front-End

The R_F amplifier and the feedback capacitor (C_F) form a low-pass filter for the input signal current. Always ensure that the low-pass filter RC time constant has sufficiently high bandwidth (as shown by Equation 1) because the input current consists of pulses. For this reason, the feedback capacitor is also programmable. Available C_F values include: 5 pF, 10 pF, 25 pF, 50 pF, 100 pF, and 250 pF. Any combination of these capacitors can also be used.

Equation 1.

The output voltage of the I-V amplifier includes the pleth component (the desired signal) and a component resulting from the ambient light leakage. The I-V amplifier is followed by the second stage, which consists of a current digital-to-analog converter (DAC) that sources the cancellation current and an amplifier that gains up the pleth component alone. The amplifier has five programmable gain settings: 0 dB, 3.5 dB, 6 dB, 9.5 dB, and
12 dB. The gained-up pleth signal is then low-pass filtered (500-Hz bandwidth) and buffered before driving a 22-bit ADC. The current DAC has a cancellation current range of 10 µA with 10 steps (1 µA each). The DAC value can be digitally specified with the SPI interface. Using ambient compensation with the ambient DAC allows the dc-biased signal to be centered to near mid-point of the amplifier (±0.9 V). Using the gain of the second stage allows for more of the available ADC dynamic range to be used.

The output of the ambient cancellation amplifier is separated into LED2 and LED1 channels. When LED2 is on, the amplifier output is filtered and sampled on capacitor C_R. Similarly, the LED1 signal is sampled on the C_LED1 capacitor when LED1 is ON. In between the LED2 and LED1 pulses, the idle amplifier output is sampled to estimate the ambient signal on capacitors C_{LED2_amb} and C_{LED1_amb}.

The sampling duration is termed the Rx sample time and is programmable for each signal, independently. Sampling can start after the I-V amplifier output is stable (to account for LED and cable settling times). The Rx sample time is used for all dynamic range calculations; the minimum time supported is 50 µs.

A single, 22-bit ADC converts the sampled LED2, LED1, and ambient signals sequentially. Each conversion takes a maximum of 25% of the pulse repetition period (PRP) and provides a single digital code at the ADC output. As discussed in the Receiver Timing section, the conversions are staggered so that the LED2 conversion starts after the end of the LED2 sample phase, and so on. This configuration also means that the Rx sample time for each signal is no greater than 25% of the pulse repetition period.

Note that four data streams are available at the ADC output (LED2, LED1, ambient LED2, and ambient LED1) at the same rate as the pulse repetition frequency. The ADC is followed by a digital ambient subtraction block that additionally outputs the (LED2 – ambient LED2) and (LED1 – ambient LED1) data values.

8.3.1.2 Ambient Cancellation Scheme

The receiver provides digital samples corresponding to ambient duration. The host processor (external to the AFE) can use these ambient values to estimate the amount of ambient light leakage. The processor must then set the value of the ambient cancellation DAC using the SPI, as shown in Figure 56.

Figure 56. Ambient Cancellation Loop (Closed by the Host Processor)

Using the set value, the ambient cancellation stage subtracts the ambient component and gains up only the pleth component of the received signal, as shown in Figure 57. The amplifier gain is programmable to 0 dB, 3.5 dB,
6 dB, 9.5 dB, and 12 dB.

Figure 57. Front-End (I-V Amplifier and Cancellation Stage)

The differential output of the second stage is V_DIFF, as given by Equation 2:

Equation 2.

where

• R_I = 100 kΩ,
• I_PLETH = photodiode current pleth component,
• I_AMB = photodiode current ambient component, and
• I_CANCEL = the cancellation current DAC value (as estimated by the host processor).

R_G values with various gain settings are listed in Table 1.

8.3.1.3 Receiver Control Signals

LED2 sample phase (S_LED2): When this signal is high, the amplifier output corresponds to the LED2 on-time. The amplifier output is filtered and sampled into capacitor C_LED2. To avoid settling effects resulting from the LED or cable, program S_LED2 to start after the LED turns on. This settling delay is programmable.

Ambient sample phase (S_{LED2_amb}): When this signal is high, the amplifier output corresponds to the LED2 off-time and can be used to estimate the ambient signal (for the LED2 phase). The amplifier output is filtered and sampled into capacitor C_{LED2_amb}.

LED1 sample phase (S_LED1): When this signal is high, the amplifier output corresponds to the LED1 on-time. The amplifier output is filtered and sampled into capacitor C_LED1. To avoid settling effects resulting from the LED or cable, program S_LED1 to start after the LED turns on. This settling delay is programmable.

Ambient sample phase (S_{LED1_amb}): When this signal is high, the amplifier output corresponds to the LED1 off-time and can be used to estimate the ambient signal (for the LED1 phase). The amplifier output is filtered and sampled into capacitor C_{LED1_amb}.

LED2 convert phase (CONV_LED2): When this signal is high, the voltage sampled on C_LED2 is buffered and applied to the ADC for conversion. The conversion time duration is always 25% of the pulse repetition period. At the end of the conversion, the ADC provides a single digital code corresponding to the LED2 sample.

Ambient convert phases (CONV_{LED2_amb}, CONV_{LED1_amb}): When this signal is high, the voltage sampled on C_{LED2_amb} (or C_{LED1_amb}) is buffered and applied to the ADC for conversion. The conversion time duration is always 25% of the pulse repetition period. At the end of the conversion, the ADC provides a single digital code corresponding to the ambient sample.

LED1 convert phase (CONV_LED1): When this signal is high, the voltage sampled on C_LED1 is buffered and applied to the ADC for conversion. The conversion time duration is always 25% of the pulse repetition period. At the end of the conversion, the ADC provides a single digital code corresponding to the LED1 sample.

8.3.1.4 Receiver Timing

See Figure 58 for a timing diagram detailing the control signals related to the LED on-time, Rx sample time, and the ADC conversion times for each channel.

NOTE: Relationship to the AFE4490EVM is: LED1 = IR and LED2 = RED.

Figure 58. Rx Timing Diagram

8.3.3.1 Using the Timer Module

The timer module registers can be used to program the start and end instants in units of 4-MHz clock cycles. These timing instants and the corresponding registers are listed in Table 2.

Note that the device does not restrict the values in these registers; thus, the start and end edges can be positioned anywhere within the pulse repetition period. Care must be taken by the user to program suitable values in these registers to avoid overlapping the signals and to make sure none of the edges exceed the value programmed in the PRP register. Writing the same value in the start and end registers results in a pulse duration of one clock cycle. The following steps describe the timer sequencing configuration:

1. With respect to the start of the PRP period (indicated by timing instant t₀ in Figure 63 and Figure 64), the sequence of conversions must be followed in order: convert LED2 → LED2 ambient → LED1 → LED1 ambient.
2. Also, starting from t₀, the sequence of sampling instants must be staggered with respect to the respective conversions as follows: sample LED2 ambient → LED1 → LED1 ambient → LED2.
3. Finally, align the edges for the two LED pulses with the respective sampling instants.

1. RED = LED2, IR = LED1.

2. A low ADC reset time can result in a small component of the LED signal leaking into the ambient phase. With an ADC reset of two clock cycles, a –60-dB leakage is expected. In many cases, this leakage does not affect system performance. However, if this crosstalk must be completely eliminated, a longer ADC reset time of approximately six clock cycles is recommended for t₂₂, t₂₄, t₂₆, and t₂₈.

Figure 63. Programmable Clock Edges⁽¹⁾⁽²⁾

1. RED = LED2, IR = LED1.

2. A low ADC reset time can result in a small component of the LED signal leaking into the ambient phase. With an ADC reset of two clock cycles, a –60-dB leakage is expected. In many cases, this leakage does not affect system performance. However, if this crosstalk must be completely eliminated, a longer ADC reset time of approximately six clock cycles is recommended for t₂₂, t₂₄, t₂₆, and t₂₈.

Figure 64. Relationship Between the ADC Reset and ADC Conversion Signals⁽¹⁾⁽²⁾

8.3.5.1 Transmitter Power Path

The block diagram in Figure 68 shows the device Tx subsystem power routing.

Figure 68. Transmit Subsystem Power Routing

8.3.5.2 LED Power Reduction During Periods of Inactivity

The diagram in Figure 69 shows how LED bias current passes 50 µA whenever LED_ON occurs. In order to minimize power consumption in periods of inactivity, the LED_ON control must be turned off. Furthermore, disable the TIMEREN bit in the CONTROL1 register by setting the value to '0'.

Note that depending on the LEDs used, the LED may sometimes appear dimly lit even when the LED current is set to 0 mA. This appearance is because of the switching leakage currents (as shown in Figure 69) inherent to the timer function. The dimmed appearance does not effect the ambient light level measurement because during the ambient cycle, LED_ON is turned off for the duration of the ambient measurement.

Figure 69. LED Bias Current

8.4.1.1 Operation Without Averaging

In this mode, the ADC outputs a digital sample one time for every 50 µs. At the next rising edge of the ADC reset signal, the first 22-bit conversion value is written into the result registers sequentially as follows (see Figure 71):

• At the 25% reset signal, the first 22-bit ADC sample is written to register 2Ah.
• At the 50% reset signal, the first 22-bit ADC sample is written to register 2Bh.
• At the 75% reset signal, the first 22-bit ADC sample is written to register 2Ch.
• At the next 0% reset signal, the first 22-bit ADC sample is written to register 2Dh. The contents of registers 2Ah and 2Bh are written to register 2Eh and the contents of registers 2Ch and 2Dh are written to register 2Fh.

At the rising edge of the ADC_RDY signal, the contents of all six result registers can be read out.

8.4.1.2 Operation With Averaging

In this mode, all ADC digital samples are accumulated and averaged after every 50 µs. At the next rising edge of the ADC reset signal, the average value (22-bit) is written into the output registers sequentially as follows (see Figure 72):

• At the 25% reset signal, the averaged 22-bit word is written to register 2Ah.
• At the 50% reset signal, the averaged 22-bit word is written to register 2Bh.
• At the 75% reset signal, the averaged 22-bit word is written to register 2Ch.
• At the next 0% reset signal, the averaged 22-bit word is written to register 2Dh. The contents of registers 2Ah and 2Bh are written to register 2Eh and the contents of registers 2Ch and 2Dh are written to register 2Fh.

At the rising edge of the ADC_RDY signal, the contents of all six result registers can be read out.

The number of samples to be used per conversion phase is specified in the CONTROL1 register (NUMAV[7:0]). The user must specify the correct value for the number of averages, as described in Equation 5:

Equation 5.

When the number of averages is '0', the averaging is disabled and only one ADC sample is written to the result registers.

Note that he number of average conversions is limited by 25% of the PRF. For example, eight samples can be averaged with PRF = 625 Hz, and four samples can be averaged with PRF = 1250 Hz.

Figure 71. ADC Data without Averaging (when Number of Averages = 0)

NOTE: Example is with three averages. The value of the NUMAVG[7:0] register bits = 2.

Figure 72. ADC Data with Averaging Enabled

8.4.3.1 Photodiode-Side Fault Detection

Figure 76 shows the diagnostic for the photodiode-side fault detection.

Figure 76. Photodiode Diagnostic

8.4.3.2 Transmitter-Side Fault Detection

Figure 77 shows the diagnostic for the transmitter-side fault detection.

Figure 77. Transmitter Diagnostic

8.4.3.3 Diagnostics Module

The diagnostics module, when enabled, checks for nine types of faults sequentially. The results of all faults are latched in 11 separate flags. At the end of the sequence, the state of the 11 flags are combined to generate two interrupt signals: PD_ALM for photodiode-related faults and LED_ALM for transmit-related faults. The status of all flags can also be read using the SPI interface. Table 3 details each fault and flag used. Note that the diagnostics module requires all AFE blocks to be enabled in order to function reliably.

Figure 78 shows the timing for the diagnostic function.

Figure 78. Diagnostic Timing Diagram

By default, the diagnostic function takes t_DIAG = 8 ms to complete after the DIAG_EN register bit is enabled. By setting the EN_SLOW_DIAG register bit (CONTROL2 register, bit D8) the diagnostic time can be increased to
16 ms.

After completion of the diagnostics function, time must be allowed for the device filter to settle. See the Electrical Characteristics for the filter settling time. The slow diagnostics feature is provided for use in systems where high-capacitance sensors (such as photodiodes, capacitors, cables, and so forth) are connected to the INP, INN, TXP, or TXN pins.

8.5.2.1 Writing Data

The SPI_READ register bit must be first set to '0' before writing to a register. When SPISTE is low,

• Serially shifting bits into the device is enabled.
• Serial data (on the SPISIMO pin) are latched at every SCLK rising edge.
• The serial data are loaded into the register at every 32nd SCLK rising edge.

In case the word length exceeds a multiple of 32 bits, the excess bits are ignored. Data can be loaded in multiples of 32-bit words within a single active SPISTE pulse. The first eight bits form the register address and the remaining 24 bits form the register data. Figure 79 shows an SPI timing diagram for a single write operation. For multiple read and write cycles, refer to the Multiple Data Reads and Writes section.

Figure 79. AFE SPI Write Timing Diagram

8.5.2.2 Reading Data

The SPI_READ register bit must be first set to '1' before reading from a register. The device includes a mode where the contents of the internal registers can be read back on the SPISOMI pin. This mode may be useful as a diagnostic check to verify the serial interface communication between the external controller and the AFE. To enable this mode, first set the SPI_READ register bit using the SPI write command, as described in the Writing Data section. In the next command, specify the SPI register address with the desired content to be read. Within the same SPI command sequence, the AFE outputs the contents of the specified register on the SPISOMI pin. Figure 80 shows an SPI timing diagram for a single read operation. For multiple read and write cycles, refer to the Multiple Data Reads and Writes section.

1. The SPI_READ register bit must be enabled before attempting a serial readout from the AFE.

2. Specify the register address of the content that must be readback on bits A[7:0].

3. The AFE outputs the contents of the specified register on the SPISOMI pin.

Figure 80. AFE SPI Read Timing Diagram^(1)(2)(3)

8.5.2.3 Multiple Data Reads and Writes

The device includes functionality where multiple read and write operations can be performed during a single SPISTE event. To enable this functionality, the first eight bits determine the register address to be written and the remaining 24 bits determine the register data. Perform two writes with the SPI read bit enabled during the second write operation in order to prepare for the read operation, as described in the Writing Data section. In the next command, specify the SPI register address with the desired content to be read. Within the same SPI command sequence, the AFE outputs the contents of the specified register on the SPISOMI pin. This functionality is described in the Writing Data and Reading Data sections. Figure 81 shows a timing diagram for the SPI multiple read and write operations.

1. The SPI read register bit must be enabled before attempting a serial readout from the AFE.

2. The second write operation must be configured for register 0 with data 000001h.

3. Specify the register address whose contents must be read back on A[7:0].

4. The AFE outputs the contents of the specified register on the SOMI pin.

Figure 81. Serial Multiple Read and Write Operations

8.5.2.4 Register Initialization

After power-up, the internal registers must be initialized to the default values. This initialization can be done in one of two ways:

• Through a hardware reset by applying a low-going pulse on the RESET pin, or
• By applying a software reset. Using the serial interface, set SW_RESET (bit D3 in register 00h) high. This setting initializes the internal registers to the default values and then self-resets to '0'. In this case, the RESET pin is kept high (inactive).

8.5.2.5 AFE SPI Interface Design Considerations

Note that when the device is deselected, the SPISOMI, CLKOUT, ADC_RDY, PD_ALM, LED_ALM, and DIAG_END digital output pins do not enter a 3-state mode. This condition, therefore, must be taken into account when connecting multiple devices to the SPI port and for power-management considerations. In order to avoid loading the SPI bus when multiple devices are connected, the DIGOUT_TRISTATE register bit must be to '1' whenever the AFE SPI is inactive.

Table 5. PD_ALM and LED_ALM Pin Settings

Table 6. Full-Scale LED Current across Tx Reference Voltage Settings⁽¹⁾