JAJSLP2A august   2021  – july 2023 AFE439A2 , AFE539A4 , AFE639D2

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  熱に関する情報
    5. 6.5  Electrical Characteristics: Voltage Output
    6. 6.6  Electrical Characteristics: Comparator Mode
    7. 6.7  Electrical Characteristics: ADC Input
    8. 6.8  Electrical Characteristics: General
    9. 6.9  Timing Requirements: I2C Standard Mode
    10. 6.10 Timing Requirements: I2C Fast Mode
    11. 6.11 Timing Requirements: I2C Fast Mode Plus
    12. 6.12 Timing Requirements: SPI Write Operation
    13. 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    14. 6.14 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    15. 6.15 Timing Requirements: PWM Output
    16. 6.16 Timing Requirements: I2C Controller
    17. 6.17 Timing Diagrams
    18. 6.18 Typical Characteristics: Voltage Output
    19. 6.19 Typical Characteristics: ADC
    20. 6.20 Typical Characteristics: Comparator
    21. 6.21 Typical Characteristics: General
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Smart Analog Front End (AFE) Architecture
      2. 7.3.2 Programming Interface
      3. 7.3.3 Nonvolatile Memory (NVM)
        1. 7.3.3.1 NVM Cyclic Redundancy Check (CRC)
          1. 7.3.3.1.1 NVM-CRC-FAIL-USER Bit
          2. 7.3.3.1.2 NVM-CRC-FAIL-INT Bit
      4. 7.3.4 Power-On Reset (POR)
      5. 7.3.5 External Reset
      6. 7.3.6 Register-Map Lock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Voltage-Output Mode
      2. 7.4.2 Voltage Reference and DAC Transfer Function
        1. 7.4.2.1 Power-Supply as Reference
        2. 7.4.2.2 Internal Reference
        3. 7.4.2.3 External Reference
      3. 7.4.3 Comparator Mode
      4. 7.4.4 Analog-to-Digital Converter (ADC) Mode
      5. 7.4.5 Pulse-Width Modulation (PWM)
      6. 7.4.6 Proportional-Integral (PI) Control
        1. 7.4.6.1 AFE439A2 PI Control
        2. 7.4.6.2 AFE539A4 PI Control
        3. 7.4.6.3 AFE639D2 PI Control
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
    6. 7.6 Register Maps
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-x-VOUT-CMP-CONFIG Register (address = 03h, 09h, 0Fh, 15h)
      3. 7.6.3  COMMON-CONFIG Register (address = 1Fh)
      4. 7.6.4  COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      5. 7.6.5  COMMON-PWM-TRIG Register (address = 21h) [reset = 0000h]
      6. 7.6.6  GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      7. 7.6.7  INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      8. 7.6.8  STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0003h]
      9. 7.6.9  STATE-MACHINE-CONFIG1 Register (address = 29h) [reset = C800h]
      10. 7.6.10 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      11. 7.6.11 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4.6.2 AFE539A4 PI Control

The AFE539A4 provides a preprogrammed PI controller state machine. Figure 7-9 shows the PI controller architecture. ADC channel 0 is used as the input and DAC channel 1 is used as the output. DAC channel 2 is used as a comparator that is used to set the output of DAC channel 1 to a value specified by the FIXED-OUTPUT field. Table 7-13 lists all the input/output pin names and functions.

GUID-20210703-CA0I-VLQW-0F4K-GJWGVTSS4BX7-low.svg Figure 7-8 PI Controller Architecture
Table 7-9 PI Controller Pin Definition
PIN FUNCTION RANGE
AIN0 ADC0 input Hi-Z: 0 V to VFS / 3
Finite impedance: 0 V to VFS
FB1 Voltage-feedback input for DAC1—connect this pin to OUT1 Not applicable
OUT1 DAC1 voltage output 0 V to VFS
AIN2 DAC2 comparator input— connect to AGND if unused for fixed output clamping See Section 7.4.3
AEN Not used for PI control—connect to VDD using a pullup resistor Not applicable

The PI controller provides many configuration parameters. Table 7-10 describes the function of each configuration parameter:

Table 7-10 PI Controller Parameters for AFE539A4: Description
REGISTER FIELD NAME STATIC ADDRESS
SETPOINT The 10-bit set point to which the ADC input is compared by the PI controller. The unit of this value is the same as the value at the ADC input. The PI controller minimizes the error between the set point and the sensed ADC data.
KP This 16-bit parameter is used as the proportional gain. KP is multiplied with the instantaneous error. A higher KP enables the loop to correct the error faster. However, if the external process has a fast response time, a higher KP can cause system instability.
KI This 16-bit parameter is used as inverse integral gain. KI is inverted and multiplied to the accumulated error. This parameter is important to help minimize the steady-state error under different ambient conditions of the process. A higher KI means a weaker response to the steady-state error. A smaller KI can effectively correct the steady-state error, but can also lead to bigger oscillations. The integral function is disabled when KI = 0.
MAX-OUTPUT This 10-bit value limits the maximum value of the PI controller output.
MIN-OUTPUT This 10-bit value limits the minimum value of the PI controller output.
COMMON-MODE This 10-bit value is present at the PI output when the proportional and integral outputs are zero. This parameter is very important to help achieve a uniform response for all set points with fixed KP and KI settings. COMMON-MODE represents the nominal output to achieve a given set point. Therefore, for best results, use empirically measured COMMON-MODE values for every set point.
LOOP-POLARITY This 1-bit parameter provides the option to invert the phase of the PI-controller loop. This function is useful when the loop external to the device has an additional phase inversion.
FIXED-OUTPUT This 10-bit parameter is used to take the output to this predefined value based on the output of comparator. This function is useful in failure scenarios.
ADC-MODE This 1-bit parameter is used to select between Hi-Z or finite-impedance mode for ADC. ADC-MODE = 0 corresponds to Hi-Z input; ADC-MODE = 1 corresponds to finite-impedance input.
CMP-THRESHOLD This 10-bit parameter is used to set the threshold for comparator.
Note: An SRAM location is accessed using the SRAM-ADDR and SRAM-DATA registers. Do not access the SRAM registers when the state machine is running. The state machine can be stopped by writing to the STATE-MACHINE-CONFIG0 register. The critical parameters that must be updated in run-time can be accessed using the dynamic locations as listed in Table 8-37. The static (SRAM) locations in Table 8-37 are mapped to NVM. The dynamic locations are not mapped to the NVM. Set all the unassigned bits in the static SRAM locations to 0.
Table 7-11 PI Controller Parameters for AFE539A4: Values
REGISTER FIELD NAME STATIC ADDRESS STATIC ADDRESS LOCATION DEFAULT VALUE (16‑BIT ALIGNED) DYNAMIC ADDRESS DYNAMIC ADDRESS LOCATION
SETPOINT 0x22[9:0] SRAM 0x0200 0x06[9:0] Register
KP 0x23[15:0] SRAM 0x0064 N/A N/A
KI 0x26[15:0] SRAM 0x0000 N/A N/A
MAX-OUTPUT 0x20[15:6] SRAM 0xFFF0 N/A N/A
MIN-OUTPUT 0x21[15:6] SRAM 0x0000 N/A N/A
COMMON-MODE 0x25[11:2] SRAM 0x02FF 0x0C[11:2] Register
LOOP-POLARITY 0x27[0] SRAM 0x0000 N/A N/A
FIXED-OUTPUT 0x27[15:6] SRAM 0x0000 N/A N/A
ADC-MODE 0x27[1] SRAM 0x0000 N/A N/A
CMP-THRESHOLD 0x24[15:6] SRAM 0x8000 N/A N/A

Table 7-16 shows the default device configuration.

Table 7-12 Device Configuration for AFE539A4
REGISTER NAME ADDRESS DEFAULT VALUE
COMMON-CONFIG 0x1F 0x1249
DAC-A-VOUT-CMP-CONFIG 0x03 0x0401
DAC-B-VOUT-CMP-CONFIG 0x09 0x0400
DAC-C-VOUT-CMP-CONFIG 0x0F 0x0405
DAC-D-VOUT-CMP-CONFIG 0x15 0x0401
STATE-MACHINE-CONFIG0 0x27 0x0003

Follow these steps to configure and operate the PI controller:

  1. Stop the state machine by writing 0004h to the STATE-MACHINE-CONFIG0 register.
  2. Connect the ADC input, comparator input, and DAC output as shown in Figure 7-9.
  3. Write to the COMMON-CONFIG register to enable all the channels.
  4. Write to the DAC-x-VOUT-CMP-CONFIG register for respective channels to select the voltage reference and output range for each channel. Configure channels A, C, and D as comparators.
  5. Calculate the voltage output range for DAC1 and configure MIN-OUTPUT and MAX-OUTPUT accordingly.
  6. Program the configuration parameters LOOP-POLARITY, ADC-MODE, CMP-THRESHOLD, and FIXED-OUTPUT as appropriate for the system.
  7. Program the initial values of KP and KI.
  8. Maintain a table to SETPOINT versus COMMON-MODE in the host processor and program these values as required by the system.
  9. Configure the STATE-MACHINE-CONFIG0 register to start the state machine.
  10. Tune the KP and KI iteratively to achieve the best transient and steady-state response.
  11. Store the values in the NVM by writing to the NVM-PROG bit in the COMMON-TRIGGER register.