JAJSLP2A august   2021  – july 2023 AFE439A2 , AFE539A4 , AFE639D2

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  熱に関する情報
    5. 6.5  Electrical Characteristics: Voltage Output
    6. 6.6  Electrical Characteristics: Comparator Mode
    7. 6.7  Electrical Characteristics: ADC Input
    8. 6.8  Electrical Characteristics: General
    9. 6.9  Timing Requirements: I2C Standard Mode
    10. 6.10 Timing Requirements: I2C Fast Mode
    11. 6.11 Timing Requirements: I2C Fast Mode Plus
    12. 6.12 Timing Requirements: SPI Write Operation
    13. 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    14. 6.14 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    15. 6.15 Timing Requirements: PWM Output
    16. 6.16 Timing Requirements: I2C Controller
    17. 6.17 Timing Diagrams
    18. 6.18 Typical Characteristics: Voltage Output
    19. 6.19 Typical Characteristics: ADC
    20. 6.20 Typical Characteristics: Comparator
    21. 6.21 Typical Characteristics: General
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Smart Analog Front End (AFE) Architecture
      2. 7.3.2 Programming Interface
      3. 7.3.3 Nonvolatile Memory (NVM)
        1. 7.3.3.1 NVM Cyclic Redundancy Check (CRC)
          1. 7.3.3.1.1 NVM-CRC-FAIL-USER Bit
          2. 7.3.3.1.2 NVM-CRC-FAIL-INT Bit
      4. 7.3.4 Power-On Reset (POR)
      5. 7.3.5 External Reset
      6. 7.3.6 Register-Map Lock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Voltage-Output Mode
      2. 7.4.2 Voltage Reference and DAC Transfer Function
        1. 7.4.2.1 Power-Supply as Reference
        2. 7.4.2.2 Internal Reference
        3. 7.4.2.3 External Reference
      3. 7.4.3 Comparator Mode
      4. 7.4.4 Analog-to-Digital Converter (ADC) Mode
      5. 7.4.5 Pulse-Width Modulation (PWM)
      6. 7.4.6 Proportional-Integral (PI) Control
        1. 7.4.6.1 AFE439A2 PI Control
        2. 7.4.6.2 AFE539A4 PI Control
        3. 7.4.6.3 AFE639D2 PI Control
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
    6. 7.6 Register Maps
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-x-VOUT-CMP-CONFIG Register (address = 03h, 09h, 0Fh, 15h)
      3. 7.6.3  COMMON-CONFIG Register (address = 1Fh)
      4. 7.6.4  COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      5. 7.6.5  COMMON-PWM-TRIG Register (address = 21h) [reset = 0000h]
      6. 7.6.6  GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      7. 7.6.7  INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      8. 7.6.8  STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0003h]
      9. 7.6.9  STATE-MACHINE-CONFIG1 Register (address = 29h) [reset = C800h]
      10. 7.6.10 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      11. 7.6.11 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-20230619-SS0I-VRH5-MPDR-6N2WXM9S1TPF-low.svg Figure 5-1 AFE639D2: RTE Package, 16-pin WQFN (Top View)
Table 5-1 Pin Functions: AFE639D2
PIN TYPE DESCRIPTION
NO. NAME
1 FB0 Input Voltage feedback input for DAC channel 0. Connect this pin to OUT0 for closed-loop amplifier output.
2 OUT0 Output Analog output for DAC channel 0.
3 NC — Not connected.
4 NC — Not connected.
5 NC/SDO/SDA2 Input/Output Target mode: This pin can be configured as SDO or left unconnected. For SDO function, connect this pin to the IO voltage with an external pullup resistor.
Controller mode: Bidirectional I2C serial data bus.
6 SCL/SYNC Input Target mode: I2C serial interface clock or SPI chip select input. Connect this pin to the IO voltage using an external pullup resistor.
7 A0/SDI/SCL2 Input/Output Target mode: Address configuration input in I2C target mode or serial data input for SPI. In A0 function, connect this pin to VDD, AGND, SDA, or SCL for address configuration. In SDI function, this pin does not need termination.
Controller mode: I2C serial interface clock output.
8 SDA/SCLK Input/Output Target mode: Bidirectional I2C serial data bus or SPI clock input. Connect this pin to the IO voltage using an external pullup resistor.
9 NC — Not connected.
10 NC — Not connected.
11 NC — Not connected.
12 AIN1 Input Analog input for comparator.
13 CAP Power External bypass capacitor for the internal LDO. Connect a capacitor (approximately 1.5 μF) between CAP and AGND.
14 AGND Ground Ground reference point for all circuitry on the device.
15 VDD Power Supply voltage: 1.8 V to 5.5 V.
16 VREF/MODE Input External reference or interface mode select input. Connect a capacitor (approximately 0.1 μF) between VREF/MODE and AGND. Use a pullup resistor to VDD when the external reference is not used. In case an external reference is used or when in interface select mode, make sure the reference ramps up after VDD. In interface select mode:
Pull this pin low to enable I2C target or SPI communication.
Pull this pin high to enable I2C controller mode.
— Thermal Pad Ground Connect the thermal pad to AGND.
GUID-20230619-SS0I-6TFV-67LD-BGWRH2P8JTNN-low.svg Figure 5-2 AFE539A4: RTE Package, 16-pin WQFN (Top View)
Table 5-2 Pin Functions: AFE539A4
PIN TYPE DESCRIPTION
NO. NAME
1 AEN Input ADC hardware enable pin. Connect this pin to VDD with a pullup resistor.
2 NC — Not connected.
3 NC — Not connected.
4 AIN2 Input Analog input to the comparator. When unused, pull this pin to VDD or AGND.
5 NC/SDO Output This pin can be configured as SDO or left unconnected. For SDO function, connect this pin to the IO voltage with an external pullup resistor.
6 SCL/SYNC Input I2C serial interface clock or SPI chip select input. Connect this pin to the IO voltage using an external pullup resistor.
7 A0/SDI Input Address configuration input for I2C or serial data input for SPI. In A0 function, connect this pin to VDD, AGND, SDA, or SCL for address configuration.
In SDI function, this pin does not need termination.
8 SDA/SCLK Input/Output Bidirectional I2C serial data bus or SPI clock input. Connect this pin to the IO voltage using an external pullup resistor.
9 FB1 Input Voltage feedback input for DAC channel 1. Connect this pin to OUT1 for closed-loop amplifier output.
10 OUT1 Output Analog output for DAC channel 1.
11 NC — Not connected.
12 AIN0 Input Analog input for ADC channel 0.
13 CAP Power External bypass capacitor for the internal LDO. Connect a capacitor (approximately 1.5 μF) between CAP and AGND.
14 AGND Ground Ground reference point for all circuitry on the device.
15 VDD Power Supply voltage: 1.8 V to 5.5 V
16 VREF/MODE Input External reference or interface mode select input. Connect a capacitor (approximately 0.1 μF) between VREF and AGND. Use a pullup resistor to VDD when the external reference is not used. In case an external reference is used or when in interface select mode, make sure the reference ramps up after VDD. In interface select mode:
Pull this pin low to enable I2C/SPI communication.
Pull this pin high to enable standalone mode.
— Thermal Pad Ground Connect the thermal pad to AGND.
GUID-20230619-SS0I-V88V-VDZM-VXCHVTT1QQLJ-low.svg Figure 5-3 AFE439A2: RTE Package, 16-pin WQFN (Top View)
Table 5-3 Pin Functions: AFE439A2
PIN TYPE DESCRIPTION
NO. NAME
1 AEN Input ADC hardware enable pin. Connect this pin to VDD with a pullup resistor.
2 AIN0 Input Analog input for ADC channel 0.
3 NC — Not connected.
4 NC — Not connected.
5 NC/SDO Output This pin can be configured as SDO or left unconnected. For SDO function, connect this pin to the IO voltage with an external pullup resistor.
6 SCL/SYNC Input I2C serial interface clock or SPI chip select input. Connect this pin to the IO voltage using an external pullup resistor.
7 A0/SDI/DIR Input Programming mode: Address configuration input for I2C or serial data input for SPI. In A0 function, connect this pin to VDD, AGND, SDA, or SCL for address configuration. In SDI function, this pin does not need termination.
Standalone mode: Direction output.
8 SDA/SCLK/PWM Input/Output Programming mode: Bidirectional I2C serial data bus or SPI clock input. Connect this pin to the IO voltage using an external pullup resistor.
Standalone mode: PWM output.
9 NC — Not connected.
10 NC — Not connected.
11 NC — Not connected.
12 AIN1 Input Analog input for comparator. When unused, pull this pin to VDD or AGND.
13 CAP Power External bypass capacitor for the internal LDO. Connect a capacitor (approximately 1.5 μF) between CAP and AGND.
14 AGND Ground Ground reference point for all circuitry on the device.
15 VDD Power Supply voltage: 1.8 V to 5.5 V
16 VREF/MODE Input External reference or interface mode select input. Connect a capacitor (approximately 0.1 μF) between VREF and AGND. Use a pullup resistor to VDD when the external reference is not used. In case an external reference is used or when in interface select mode, make sure the reference ramps up after VDD. In interface select mode:
Pull this pin low to enable I2C/SPI communication.
Pull this pin high to enable standalone mode.
— Thermal Pad Ground Connect the thermal pad to AGND.