JAJSQK1 july   2023 AFE539F1-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: ADC Input
    6. 6.6  Electrical Characteristics: General
    7. 6.7  Timing Requirements: I2C Standard Mode
    8. 6.8  Timing Requirements: I2C Fast Mode
    9. 6.9  Timing Requirements: I2C Fast Mode Plus
    10. 6.10 Timing Requirements: SPI Write Operation
    11. 6.11 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    12. 6.12 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    13. 6.13 Timing Requirements: PWM Output
    14. 6.14 Timing Diagrams
    15. 6.15 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Analog Front End (AFE) Architecture
      2. 7.3.2 Programming Interface
      3. 7.3.3 Nonvolatile Memory (NVM)
        1. 7.3.3.1 NVM Cyclic Redundancy Check (CRC)
          1. 7.3.3.1.1 NVM-CRC-FAIL-USER Bit
          2. 7.3.3.1.2 NVM-CRC-FAIL-INT Bit
      4. 7.3.4 Power-On Reset (POR)
      5. 7.3.5 External Reset
      6. 7.3.6 Register-Map Lock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Analog-to-Digital Converter (ADC) Mode
        1. 7.4.1.1 Voltage Reference Selection
          1. 7.4.1.1.1 Power-Supply as Reference
          2. 7.4.1.1.2 Internal Reference
          3. 7.4.1.1.3 External Reference
      2. 7.4.2 Pulse-Width Modulation (PWM) Mode
      3. 7.4.3 Constant Power-Dissipation Control
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
    6. 7.6 Register Maps
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  REF-GAIN-CONFIG Register (address = 15h) [reset = 0401h]
      3. 7.6.3  COMMON-CONFIG Register (address = 1Fh) [reset = 13FFh]
      4. 7.6.4  COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      5. 7.6.5  COMMON-PWM-TRIG Register (address = 21h) [reset = 0001h]
      6. 7.6.6  GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      7. 7.6.7  INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      8. 7.6.8  STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0003h]
      9. 7.6.9  SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      10. 7.6.10 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
      11. 7.6.11 MAX-OUTPUT Register (SRAM address = 20h) [reset = 007Fh]
      12. 7.6.12 MIN-OUTPUT Register (SRAM address = 21h) [reset = 0000h]
      13. 7.6.13 FUNCTION-COEFFICIENT Register (SRAM address = 22h) [reset = 01F4h]
      14. 7.6.14 PWM-FREQUENCY Register (SRAM address = 23h) [reset = 000Bh]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4.3 Constant Power-Dissipation Control

The AFE539F1-Q1 can be used in applications where constant power dissipation is desired on a resistive load independently on applied voltage. Power dissipation in a fixed resistive load is inversely proportional to the resistance. When the voltage across the resistance varies, for example, in a discharging circuit, constant power can be achieved by modulating the effective resistance seen by the discharge circuit. Figure 7-4 shows an example circuit to create a variable effective resistance from a fixed resistive load using a PWM signal. The effective resistance is the load resistance divided by the PWM duty cycle.

GUID-20230315-SS0I-PHNC-B2CT-JXQZKVJQXKVG-low.svg Figure 7-4 PWM-modulated Resistor

The AFE539F1-Q1 generates a PWM signal with a duty cycle dependent on the voltage applied to the ADC input. The AFE539F1-Q1 has a 10-bit ADC input with selectable reference voltage (VREF). The AFE539F1-Q1 calculates the PWM duty cycle so that a constant dissipated power of the resistor is maintained.

The AFE539F1-Q1 runs a PWM duty cycle update loop that sets the duty cycle (D) according to Equation 2.

Equation 2. D = K × 2 15 A D C _ D A T A 2 = K × V F S 2 V I N 2 × 2 5

where:

  • ADC_DATA is the decimal equivalent of the output from the ADC available to the state machine.
  • VIN is the ADC input voltage.
  • VFS is the full-scale ADC input voltage, as listed in Table 7-1.
  • K is a user-configurable function-coefficient with a value of 16-bit integer (range: 1 to 65535) as programmed in the FUNCTION-COEFFICIENT register.

The duty cycle of the PWM output of the AFE539F1-Q1 has 7-bit resolution which means the minimum duty cycle as well as the step size is about 0.78%. The PWM can achieve 100% saturation, the lower and upper PWM value limit is user-configurable as well to accommodate specific application requirements. The constant power achieved with this pulse-width modulated resistor can be expressed accordingly as Equation 3.

Equation 3. P c o n s t = K 2 × V F S 2 R L

where:

  • RL is the load resistance.
  • K2 is a constant that is a function of the function-coefficient, K and the attenuation factor between the bus voltage and the full-scale ADC input.

Equation 3 expresses that the theoretical constant power is independent on the input voltage. The power depends on the load resistance value and value of the constant, K2. However, the PWM is updated in discrete steps, the calculated constant power is in reality a power limit.