SLOS729D October   2011  – November 2015 AFE5808A

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Digital Characteristics
    7. 7.7  Switching Characteristics
    8. 7.8  Timing Requirements
    9. 7.9  Output Interface Timing
    10. 7.10 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Low-Noise Amplifier (LNA)
      2. 8.3.2 Voltage-Controlled Attenuator
      3. 8.3.3 Programmable Gain Amplifier
      4. 8.3.4 Analog-to-Digital Converter
      5. 8.3.5 Continuous-Wave (CW) Beamformer
        1. 8.3.5.1 16 × ƒcw Mode
        2. 8.3.5.2 8 × ƒcw and 4 × ƒcw Modes
        3. 8.3.5.3 1 × ƒcw Mode
      6. 8.3.6 Equivalent Circuits
      7. 8.3.7 LVDS Output Interface Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 TGC Mode
      2. 8.4.2 CW Mode
      3. 8.4.3 TGC + CW Mode
      4. 8.4.4 Test Modes
        1. 8.4.4.1 ADC Test Modes
        2. 8.4.4.2 VCA Test Mode
      5. 8.4.5 Power Management
        1. 8.4.5.1 Power and Performance Optimization
        2. 8.4.5.2 Power Management Priority
        3. 8.4.5.3 Partial Power Up and Power Down Mode
        4. 8.4.5.4 Complete Power-Down Mode
        5. 8.4.5.5 Power Saving in CW Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Register Timing
        1. 8.5.1.1 Serial Register Write Description
        2. 8.5.1.2 Register Readout Description
    6. 8.6 Register Maps
      1. 8.6.1 ADC Register Map
      2. 8.6.2 ADC Register/Digital Processing Description
        1. 8.6.2.1  AVERAGING_ENABLE: Address: 2[11]
        2. 8.6.2.2  ADC_OUTPUT_FORMAT: Address: 4[3]
        3. 8.6.2.3  DIGITAL_GAIN_ENABLE: Address: 3[12]
        4. 8.6.2.4  DIGITAL_HPF_ENABLE
        5. 8.6.2.5  DIGITAL_HPF_FILTER_K_CHX
        6. 8.6.2.6  LOW_FREQUENCY_NOISE_SUPPRESSION: Address: 1[11]
        7. 8.6.2.7  LVDS_OUTPUT_RATE_2X: Address: 1[14]
        8. 8.6.2.8  CHANNEL_OFFSET_SUBSTRACTION_ENABLE: Address: 3[8]
        9. 8.6.2.9  SERIALIZED_DATA_RATE: Address: 3[14:13]
        10. 8.6.2.10 TEST_PATTERN_MODES: Address: 2[15:13]
        11. 8.6.2.11 SYNC_PATTERN: Address: 10[8]
      3. 8.6.3 VCA Register Map
      4. 8.6.4 AFE5808A VCA Register Description
        1. 8.6.4.1 LNA Input Impedances Configuration (Active Termination Programmability)
        2. 8.6.4.2 Programmable Gain for CW Summing Amplifier
        3. 8.6.4.3 Programmable Phase Delay for CW Mixer
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 LNA Configuration
          1. 9.2.2.1.1 LNA Input Coupling and Decoupling
          2. 9.2.2.1.2 LNA Noise Contribution
          3. 9.2.2.1.3 Active Termination
          4. 9.2.2.1.4 LNA Gain Switch Response
        2. 9.2.2.2 Voltage-Controlled-Attenuator
        3. 9.2.2.3 CW Operation
          1. 9.2.2.3.1 CW Summing Amplifier
          2. 9.2.2.3.2 CW Clock Selection
          3. 9.2.2.3.3 CW Supporting Circuits
        4. 9.2.2.4 ADC Operation
          1. 9.2.2.4.1 ADC Clock Configurations
          2. 9.2.2.4.2 ADC Reference Circuit
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
      1. 9.3.1 Driving the Inputs (Analog or Digital) Beyond the Power-Supply Rails
      2. 9.3.2 Driving the Device Signal Input With an Excessively High Level Signal
      3. 9.3.3 Driving the VCNTL Signal With an Excessive Noise Source
      4. 9.3.4 Using a Clock Source With Excessive Jitter, an Excessively Long Input Clock Signal Trace, or Having Other Signals Coupled to the ADC or CW Clock Signal Trace
      5. 9.3.5 LVDS Routing Length Mismatch
      6. 9.3.6 Failure to Provide Adequate Heat Removal
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

10 Power Supply Recommendations

In a mixed-signal system design, power supply and grounding design plays a significant role. The AFE5808A device distinguishes between two different grounds: AVSS (analog ground) and DVSS (digital ground). In most cases, it should be adequate to lay out the printed-circuit-board (PCB) to use a single ground plane for the AFE5808A device. Take care to partition this ground plane properly between various sections within the system to minimize interactions between analog and digital circuitry. Alternatively, the digital (DVDD) supply set consisting of the DVDD and DVSS pins can be placed on separate power and ground planes. For this configuration, the AVSS and DVSS grounds should be tied together at the power connector in a star layout. In addition, optical isolator or digital isolators, such as ISO7240, can separate the analog portion from the digital portion completely. Consequently they prevent digital noise to contaminate the analog portion. Table 2 lists the related circuit blocks for each power supply. Recommended power up sequence is shown in Figure 93.

AFE5808A pwr_up_tim_los688.gif
10 µs < t1 < 50 ms, 10 µs < t2 < 50 ms, –10 ms < t3 < 10 ms, t4 > 10 ms, t5 > 100 ns, t6 > 100 ns, t7 > 10 ms, and t8 > 100 µs.
The AVDDx and DVDD power-on sequence does not matter as long as –10 ms < t3 < 10 ms. Similar considerations apply while shutting down the device.
Figure 93. Recommended Power-up Sequencing and Reset Timing

Table 17. Supply vs Circuit Blocks

POWER SUPPLY GROUND CIRCUIT BLOCKS
AVDD (3.3VA) AVSS LNA, attenuator, PGA with current clamp and BPF, reference circuits, CW summing amplifier, CW mixer, VCA SPI
AVDD_5V (5VA) AVSS LNA, CW clock circuits, reference circuits
AVDD_ADC (1.8VA) AVSS ADC analog and reference circuits
DVDD (1.8VD) DVSS LVDS and ADC SPI

All bypassing and power supplies for the AFE5808A should be referenced to their corresponding ground planes. All supply pins should be bypassed with 0.1-µF ceramic chip capacitors (size 0603 or smaller). To minimize the lead and trace inductance, the capacitors should be located as close to the supply pins as possible. Where double-sided component mounting is allowed, these capacitors are best placed directly under the package. In addition, larger bipolar decoupling capacitors 2.2 µF to 10 µF, effective at lower frequencies) may also be used on the main supply pins. These components can be placed on the PCB in proximity (< 0.5 inch or 12.7 mm) to the AFE5808A device itself.

The AFE5808A device has a number of reference supplies needed to be bypassed, such as CM_BYP, and VHIGH. These pins should be bypassed with at least 1 µF; higher value capacitors can be used for better low-frequency noise suppression. For best results, choose low-inductance ceramic chip capacitors (size 0402, > 1 µF) and place them as close as possible to the device pins.

High-speed mixed signal devices are sensitive to various types of noise coupling. One primary source of noise is the switching noise from the serializer and the output buffer/drivers. For the AFE5808A device, the interaction between the analog and digital supplies within the device is ensured to keep to a minimal amount. The extent of noise coupled and transmitted from the digital and analog sections depends on the effective inductances of each of the supply and ground connections. Smaller effective inductance of the supply and ground pins leads to improved noise suppression. For this reason, multiple pins are used to connect each supply and ground sets. Take care to maintain low inductance properties throughout the design of the PCB layout by using proper planes and layer thickness.