SLOS738E September   2012  – August 2015 AFE5809

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Digital Demodulator Electrical Characteristics
    7. 7.7  Digital Characteristics
    8. 7.8  Switching Characteristics
    9. 7.9  SPI Switching Characteristics
    10. 7.10 Output Interface Timing Requirements (14-bit)
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 LNA
      2. 8.3.2 Voltage-Controlled Attenuator
      3. 8.3.3 PGA
      4. 8.3.4 ADC
      5. 8.3.5 Continuous-Wave (CW) Beamformer
        1. 8.3.5.1 16 × ƒcw Mode
        2. 8.3.5.2 8 × ƒcw and 4 × ƒcw Modes
        3. 8.3.5.3 1 × ƒcw Mode
      6. 8.3.6 Digital I/Q Demodulator
      7. 8.3.7 Equivalent Circuits
      8. 8.3.8 LVDS Output Interface Description
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI) Operation
        1. 8.5.1.1 ADC/VCA Serial Register Write Description
        2. 8.5.1.2 ADC/VCA Serial Register Readout Description
        3. 8.5.1.3 Digital Demodulator SPI Description
    6. 8.6 Register Maps
      1. 8.6.1 ADC and VCA Register Description
        1. 8.6.1.1 ADC Register Map
        2. 8.6.1.2 AFE5809 ADC Register/Digital Processing Description
          1. 8.6.1.2.1  AVERAGING_ENABLE: Address: 2[11]
          2. 8.6.1.2.2  ADC_OUTPUT_FORMAT: Address: 4[3]
          3. 8.6.1.2.3  ADC Reference Mode: Address 1[13] and 3[15]
          4. 8.6.1.2.4  DIGITAL_GAIN_ENABLE: Address: 3[12]
          5. 8.6.1.2.5  DIGITAL_HPF_ENABLE
          6. 8.6.1.2.6  DIGITAL_HPF_FILTER_K_CHX
          7. 8.6.1.2.7  LOW_FREQUENCY_NOISE_SUPPRESSION: Address: 1[11]
          8. 8.6.1.2.8  LVDS_OUTPUT_RATE_2X: Address: 1[14]
          9. 8.6.1.2.9  CHANNEL_OFFSET_SUBSTRACTION_ENABLE: Address: 3[8]
          10. 8.6.1.2.10 SERIALIZED_DATA_RATE: Address: 3[14:13]
          11. 8.6.1.2.11 TEST_PATTERN_MODES: Address: 2[15:13]
          12. 8.6.1.2.12 SYNC_PATTERN: Address: 10[8]
        3. 8.6.1.3 VCA Register Map
        4. 8.6.1.4 VCA Register Description
          1. 8.6.1.4.1 LNA Input Impedances Configuration (Active Termination Programmability)
          2. 8.6.1.4.2 Programmable Gain for CW Summing Amplifier
          3. 8.6.1.4.3 Programmable Phase Delay for CW Mixer
      2. 8.6.2 Digital Demodulator Register Description
        1. 8.6.2.1 Profile RAM and Coefficient RAM
          1. 8.6.2.1.1 Programming the Profile RAM
          2. 8.6.2.1.2 Procedure for Configuring Next Profile Vector
          3. 8.6.2.1.3 Programming the Coefficient RAM
          4. 8.6.2.1.4 Filter Coefficent Test Mode
          5. 8.6.2.1.5 TX_SYNC and SYNC_WORD Timing
          6. 8.6.2.1.6 FIR Filter Delay versus TX_TRIG Timing
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 LNA Configuration
          1. 9.2.2.1.1 LNA Input Coupling and Decoupling
          2. 9.2.2.1.2 LNA Noise Contribution
          3. 9.2.2.1.3 Active Termination
          4. 9.2.2.1.4 LNA Gain Switch Response
        2. 9.2.2.2 Voltage-Controlled Attenuator
        3. 9.2.2.3 CW Operation
          1. 9.2.2.3.1 CW Summing Amplifier
          2. 9.2.2.3.2 CW Clock Selection
          3. 9.2.2.3.3 CW Supporting Circuits
        4. 9.2.2.4 Low Frequency Support
        5. 9.2.2.5 ADC Operation
          1. 9.2.2.5.1 ADC Clock Configurations
          2. 9.2.2.5.2 ADC Reference Circuit
      3. 9.2.3 Application Curves
    3. 9.3 System Example
      1. 9.3.1 ADC Debug
      2. 9.3.2 VCA Debug
    4. 9.4 Do's and Don'ts
      1. 9.4.1 Driving the Inputs (Analog or Digital) Beyond the Power-Supply Rails
      2. 9.4.2 Driving the Device Signal Input With an Excessively High Level Signal
      3. 9.4.3 Driving the VCNTL Signal With an Excessive Noise Source
      4. 9.4.4 Using a Clock Source With Excessive Jitter, an Excessively Long Input Clock Signal Trace, or Having Other Signals Coupled to the ADC or CW Clock Signal Trace
      5. 9.4.5 LVDS Routing Length Mismatch
      6. 9.4.6 Failure to Provide Adequate Heat Removal
  10. 10Power Supply Recommendations
    1. 10.1 Power/Performance Optimization
    2. 10.2 Power Management Priority
    3. 10.3 Partial Power-Up and Power-Down Mode
    4. 10.4 Complete Power-Down Mode
    5. 10.5 Power Saving in CW Mode
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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4 Revision History

Changes from D Revision (January 2014) to E Revision

  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
  • Changed N4 and N6 to " When LDO_EN L4 = 1.8 V, demodulator digital power supply generated internally. These two pins should be separated on the PCB and decoupled respectively with 0.1-µF capacitors. When LDO_EN L4=DVSS, the internal LDOs are disabled. External higher performance 1.4-V supply can be applied to N4 and N6 for minimizing digital noise emission. " Go
  • Changed L6 pin description to " Enable/Disable AFE's internal LDO regulators. When it is tied to 1.8-V DVDD or Logic "1", AFE's internal LDO is enabled. When it is tied to DVSS or Logic "0", AFE's internal LDO is disabled and external 1.4V supply can be applied at N4 and N6 pins, that is, DVDD_LDO1, DVDD_LDO2. " Go
  • Changed M6 pin description to "Sets the internal LDO votlage. Logic "1" or tie to 1.8-V DVDD sets the LDO output as 1.4V. It can be tied to DVSS when the internal LDO is disabled. " Go
  • Added a note to pin H8 "When the complete power-down mode is enabled, the digital demodulator may lose register settings. Therefore it is required to reconfigure the demodulator registers, filter coefficient memory and profile memory after existing the complete power-down mode. " Go
  • Added a note to pin L7 "Note: TX_SYNC signal must be synchronized with ADC CLK. Typically pulse repetition frequency (PRF) signal can be used for TX_SYNC_IN. " Go
  • Added "DVDD_LDO1/2 (external supplied)" in Recommended Operating ConditionsGo
  • Added LDO_EN VIH, VIL,IIH,IIL in Digital Demodulator Electrical CharacteristicsGo
  • Deleted "(for output data and frame clock)"Go
  • Added a note "TI recommends to synchronize SCLK to ADC CLK... " Go
  • Added a note to Register 0 [0]"Register 0 is a write only register." Go
  • Added a note to Register 0[1] "When this bit is set to 0, device will always operate in write mode; and when it is set to 1, device will be in read mode. Multiple reading or writing events can be performed when this bit is set to 1 or 0 correspondingly. Register 0 is a write only register." Go
  • Added a note "When the complete power-down mode is enabled, the digital demodulator may lose register settings. Therefore it is required to reconfigure the demodulator registers, filter coefficient memory and profile memory after existing the complete power down mode. " Go
  • Added a note to Register 3[7:0] "Suppose device is giving digital output of "11001100001111". After enabling this bit, output of device will become "00110011110000". Please note this function is not applicable for ADC test patterns and in demod mode." Go
  • Added "Test pattern from the ADC output stage can NOT be sent to the demodulator; it can only be sent to the LVDS serializer when the demodulator is off. " to TEST_PATTERN_MODES: Address: 2[15:13]Go
  • Added a note for Reg.0x3D[15] " Note: This bit is ONLY valid when PGA=24dB." Go
  • Changed Demod Reg0xA[12] to DHPF. Go
  • Added Notes to the demod Reg0x14~17"DC_REMOVAL_X_X registers are write-only" Go
  • Move "RF Mode" before Table 12.Go
  • Added Shifted output figures when DEC_SHIFT_SCALE=0 or 1Go
  • Added note "A trigger is required to make new settings effective, such as profile RAM, coefficient RAM, and PROFILE_INDX Reg.0x0E[15:11] —either an external trigger event through the TX_SYNC_IN pin or a manual trigger event through Register 0[2]. PROFILE_INDX Reg.0x0E[15:11] must be reprogrammed to ensure new profile and filter RAMs loaded correctly. ADC CLK is required during profile and coefficent RAM programming. "in Profile RAM and Coefficient RAMGo
  • Added "when DC_REMOVAL_BYPASS 10[0] = 0" to the caption of Figure 92 "Go
  • Changed " sample followed after sync word" to "demod output after sync word" .Go
  • Corrected Equation 9Go
  • Corrected Equation 10Go
  • Corrected Equation 11Go
  • Added Figure 103.Go
  • Added "CM_BYP=1.5V" in Figure 106Go
  • Added System ExampleGo
  • Moved Figure 113 to Power Supply Recommendations and added "When the demodulator power DVDD_LDO1 and DVDD_LDO2 are supplied externally, it should be powered up 1ms after DVDD. LDOs for external DVDD_LDO1 and DVDD_LDO2 can be powered down if the demodualtor is not used"Go
  • Deleted "The digital demodulator also has four power-down controls... in Power Management Priority" Go
  • Added a note "When the complete power-down mode is enabled, the digital demodulator may lose register settings. Therefore, it is required to reconfigure the demodulator registers, filter coefficient memory, and profile memory after exiting the complete power-down mode. " Go
  • Edited Layout Guidelines: "To avoid noise coupling through supply pins, it is recommended to keep sensitive input net classes, such as INM, INP, ACT pins, away from AVDD 3.3 V, AVDD_5V, DVDD, AVDD_ADC, DVDD_LDO1/2 nets or planes. For example, vias connected to these pins should NOT be routed across any supply plane. That is to avoid power planes under INM, INP, and ACT pins. "Go

Changes from C Revision (January 2013) to D Revision

  • Changed Feature: Decimation Filter Factor M = 1 to 64To: ...M = 1 to 32Go
  • Added a note for new silicon features.Go
  • Changed pin description of CLKM_16X from "In the 1× CW clock mode, this pin becomes the quadrature-phase 1× CLKM for the CW mixer" to "... in-phase 1× CLKM for the CW mixer"Go
  • Changed pin description of CLKP_16X from "In the 1× CW clock mode, this pin becomes the quadrature-phase 1× CLKP for the CW mixer" to "... in-phase 1× CLKP for the CW mixer"Go
  • Changed pin description of CLKM_1X from "In the 1× CW clock mode, this pin becomes the in-phase 1× CLKP for the CW mixer" to "... quadrature-phase 1× CLKP for the CW mixer"Go
  • Changed pin description of CLKP_1X from "In the 1× CW clock mode, this pin becomes the in-phase 1× CLKP for the CW mixer" to "... quadrature-phase 1× CLKP for the CW mixer"Go
  • Corrected AVDD_5V current from 16.5 mA to 26 mAGo
  • Changed 64× decimation factor to 32× decimation factor in DVDD consumption at 65 MSPS in Digital Demodulator Electrical CharacteristicsGo
  • Changed 64× decimation factor to 32× decimation factor in DVDD consumption at 40 MSPS in Digital Demodulator Electrical CharacteristicsGo
  • Changed Input Clock to Bit ClockGo
  • Changed Input Clock to Bit ClockGo
  • Corrected a typo in Reg0x2[15:13], that is changed 0x2[15:3] to 0x2[15:13]Go
  • Added a note to Reg0x15[0] "This HPF feature is only avaiable when the demodulation block is disabled." Go
  • Added a note to Reg0x21[0] "This HPF feature is only available when the demodulation block is disabled." Go
  • Added a note "These digital processing features are only available when the demodulation block is disabled." Go
  • Added a note in the Register 51[3:1] description,"Note: 0x3D[14], that is, 5 MHz LPF, should be set a 0. " Go
  • Added a note in the Register 57[7:5] description,"Note: Register 61[15] should be set as 0; otherwise PGA_CLAMP_LEVEL is affected by Register 61[15]." Go
  • Added Register 61[15:13] description.Go
  • Added and reorganized Description of LNA Input Impedances ConfigurationGo
  • Added Table 7Go
  • Added a note for Reg0x1F[5:0] "it is from 1 to 32."Go
  • Changed "0x521" to "0x121F" in Go
  • Changed "MODULATE_BYPASS = 1" to "MODULATE_BYPASS = 0" in Go
  • Highlighted the note about Channel Selection.Go
  • Added Figure 87Go
  • Added "FIR Filter Delay versus TX_TRIG Timing" and "Expression of Decimation Filter Response"Go
  • Updated figure reference and added a link in Expression of Decimation Filter Response.Go
  • Added text " In high channel count premium systems, the VCNTLM/P noise requirement is higher."Go
  • Added "to avoid power planes under INM, INP, and ACT pins."Go

Changes from B Revision (September 2012) to C Revision

  • Added a note "The above timing data can be applied to 12-bit or 16-bit LVDS rates"Go
  • Changed 'SIN' to '–SIN' and 'C8' to 'Cn' in Figure 61Go
  • Added "The maximum PGA output level can be above 2 Vpp even with the clamp circuit enabled" in the PGA description.Go
  • Added a note "The local oscillator inputs of the passive mixer are cos(ωt) for I-CH and sin(ωt) for Q-CH"Go
  • Changed "10 Ω" to "10 to 15 Ω " in Figure 67Go
  • Added a note "The digital demodulator is based on a conventional down converter, that is, –sin(ω0t) is used for Q phase. Go
  • Changed SPI pulldown resistors from "100 kΩ" to "20 kΩ".Go
  • Added a note to register 0x3[14:13] "Make sure the settings aligning with the demod register 0x3[14:13]" Go
  • Added Note to PGA_CLAMP_LEVEL: "The maximum PGA output level can exceed 2Vpp with the clamp circuit enabled.". Go
  • Changed from "For RF mode (passing 14 bits only)... 0xC3[14:13] to ‘00’ " to "...0xC3[14:13] to ‘10’ " in Go
  • Changed List item From: "The internal 32-bit filter output" To: The internal 36-bit filter output" Go
  • Changed text following Table 21 From: "the block index, from 0 to (–1)" To: "the block index, from 0 to (M – 1) Go
  • Added text "TI recommends that VCNTLM/P noise is below 25 nV/rtHz at 1 kHz and 5 nV/rtHz at 50 kHz. "Go
  • Added a note "The local oscillator inputs of the passive mixer are cos(ωt) for I-CH and sin(ωt) for Q-CH " Go
  • Added "AVDD_5V needs to be away from sensitive input pins"Go

Changes from A Revision (September 2012) to B Revision

  • Deleted Feature: "Programmable Digital I/Q Demodulator"Go
  • Changed Feature: Noise, Power Optimizations (Without Digital Demodulator) From: 99 mW/CH at 1.1 nV/rtHz, 40 MSPS To: 101 mW/CH at 1.1 nV/rtHz, 40 MSPSGo
  • Changed Feature: Excellent Device-to-Device Gain Matching From: ±0.5 dB (typical) and ±0.9 dB (max) To: ±0.5 dB (typical) and ±1 dB (max)Go
  • Changed Gain matching values From MIN = –0.9 dB to MIN = –1 dB and From: MAX = 0.9 dB to MAX = 1 dB Go
  • Added Note: "In the low power and medium-power modes, PGA_CLAMP is disabled for saving power if 51[7] = 0"Go
  • Added a note to PGA_CLAMP_LEVEL: "in the low-power and medium-power modes, PGA_CLAMP is disabled for saving power if 51[7] = 0"Go

Changes from * Revision (September 2012) to A Revision

  • Changed the device From: Product Preview To: ProductionGo