JAJSLP2A august   2021  – july 2023 AFE439A2 , AFE539A4 , AFE639D2

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  熱に関する情報
    5. 6.5  Electrical Characteristics: Voltage Output
    6. 6.6  Electrical Characteristics: Comparator Mode
    7. 6.7  Electrical Characteristics: ADC Input
    8. 6.8  Electrical Characteristics: General
    9. 6.9  Timing Requirements: I2C Standard Mode
    10. 6.10 Timing Requirements: I2C Fast Mode
    11. 6.11 Timing Requirements: I2C Fast Mode Plus
    12. 6.12 Timing Requirements: SPI Write Operation
    13. 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    14. 6.14 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    15. 6.15 Timing Requirements: PWM Output
    16. 6.16 Timing Requirements: I2C Controller
    17. 6.17 Timing Diagrams
    18. 6.18 Typical Characteristics: Voltage Output
    19. 6.19 Typical Characteristics: ADC
    20. 6.20 Typical Characteristics: Comparator
    21. 6.21 Typical Characteristics: General
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Smart Analog Front End (AFE) Architecture
      2. 7.3.2 Programming Interface
      3. 7.3.3 Nonvolatile Memory (NVM)
        1. 7.3.3.1 NVM Cyclic Redundancy Check (CRC)
          1. 7.3.3.1.1 NVM-CRC-FAIL-USER Bit
          2. 7.3.3.1.2 NVM-CRC-FAIL-INT Bit
      4. 7.3.4 Power-On Reset (POR)
      5. 7.3.5 External Reset
      6. 7.3.6 Register-Map Lock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Voltage-Output Mode
      2. 7.4.2 Voltage Reference and DAC Transfer Function
        1. 7.4.2.1 Power-Supply as Reference
        2. 7.4.2.2 Internal Reference
        3. 7.4.2.3 External Reference
      3. 7.4.3 Comparator Mode
      4. 7.4.4 Analog-to-Digital Converter (ADC) Mode
      5. 7.4.5 Pulse-Width Modulation (PWM)
      6. 7.4.6 Proportional-Integral (PI) Control
        1. 7.4.6.1 AFE439A2 PI Control
        2. 7.4.6.2 AFE539A4 PI Control
        3. 7.4.6.3 AFE639D2 PI Control
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
    6. 7.6 Register Maps
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-x-VOUT-CMP-CONFIG Register (address = 03h, 09h, 0Fh, 15h)
      3. 7.6.3  COMMON-CONFIG Register (address = 1Fh)
      4. 7.6.4  COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      5. 7.6.5  COMMON-PWM-TRIG Register (address = 21h) [reset = 0000h]
      6. 7.6.6  GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      7. 7.6.7  INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      8. 7.6.8  STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0003h]
      9. 7.6.9  STATE-MACHINE-CONFIG1 Register (address = 29h) [reset = C800h]
      10. 7.6.10 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      11. 7.6.11 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2 Detailed Design Procedure

This design example uses the TPS63020, a buck-boost converter, and connects the TEC element between the VIN and VOUT nodes to create bidirectional voltage control of the TEC element. The control voltage to the TPS63020 must be between 0 V and 1.8 V to achieve the full range of TEC current. As shown in Figure 8-1, the temperature is measured using the LMT70, a high-precision, analog temperature sensor. The LMT70 provides a voltage output between 1.38 V and 300 mV for the temperature range of –55ºC to +125ºC. Therefore, configure the PI controller output (DAC1) with the internal reference and a gain of 1.5 ×. Similarly, configure ADC0 to be in Hi-Z input mode (ADC-MODE = 0), with the internal reference, and 4 × gain. This configuration sets ADC0 at a full-scale input (VFS) range of (1.21 V × 4) / 3 = 1.613 V. With 10-bit resolution, 1 LSB of ADC0 code corresponds to (1.613 V / 1024) = 1.58 mV. The response slope of the LMT70 at 30ºC is 5.194 mV/ºC. Therefore, 1 LSB of the ADC0 corresponds to (1.58 / 5.194) = 0.3ºC.

The voltage output of the LMT70 corresponding to the temperature set point of 30ºC is 943.227 mV. Using Equation 4, calculate the SETPOINT input as 598d (0x256). For negative feedback, use an odd number of phase inversions in the feedback loop. The DAC1 output to the TPS63020 output has one phase inversion; the TPS63020 decreases when the DAC1 output increases. The TPS63020 output and the TEC cold-side temperature have the second phase inversion; the TEC cold-side temperature decreases when the TPS63020 output increases. The TEC cold-side and the LMT70 have the third phase inversion; when the TEC cold-side temperature decreases, the LMT70 output voltage increases. The external loop of the AFEx39xx has an odd number of phase inversions; therefore, make sure that the internal PI control loop has no phase inversion. To prevent the phase inversion, configure LOOP-POLARITY = 1. Choose the values of RF and CF in Figure 8-1 based on the noise level present in the sensing circuit.

When the output of the comparator is low, the PI controller output enters safe mode. Therefore, the current sense amplifier and the comparator setting must be configured to trigger fallback mode at the desired TEC current limit.

Follow the procedure described in Section 7.4.6.2 to configure the parameters listed in Table 8-37.

Table 8-2 PI Controller Parameters
REGISTER FIELD NAME STATIC ADDRESS STATIC ADDRESS LOCATION CONFIGURED VALUE (16-BIT) DYNAMIC ADDRESS DYNAMIC ADDRESS LOCATION
SETPOINT 0x22[9:0] SRAM 0x0256 0x06[9:0] Register
KP 0x23[15:0] SRAM 0x0FA0 N/A N/A
KI 0x26[15:0] SRAM 0x0001 N/A N/A
MAX-OUTPUT 0x20[15:6] SRAM 0xFFC0 N/A N/A
MIN-OUTPUT 0x21[15:6] SRAM 0x0000 N/A N/A
COMMON-MODE 0x25[11:2] SRAM 0x7FC0 0x0C[11:2] Register
LOOP-POLARITY 0x27[0] SRAM 0x0001 N/A N/A
FIXED-OUTPUT 0x27[15:6] SRAM 0x0000 N/A N/A
ADC-MODE 0x27[1] SRAM 0x0002 N/A N/A
CMP-THRESHOLD 0x24[15:6] SRAM 0x7FC0 N/A N/A