HART bus communication activity is reported to the host controller through the IRQ signal routed to the UARTOUT pin and MODEM_STATUS register. Read the MODEM_STATUS register to determine the source of the IRQ when an IRQ is received. If the UARTOUT pin is not connected, poll the status registers regularly through the SPI.

To transmit data, set up the desired FIFO_U2H level thresholds using FIFO_CFG.U2H_LEVEL_SET. Assert the RTS. After CTS_ASSERT is set, begin to fill FIFO_U2H. Enqueue enough data into FIFO_U2H to fill the FIFO above the set threshold level. The HART modulator automatically dequeues the data from FIFO_U2H and transmits the data on MOD_OUT. When FIFO_U2H level drops below the set threshold, an IRQ triggers, indicating that new data bytes can be enqueued without losing any data. After the last set of data have been enqueued into FIFO_U2H, an IRQ event triggered by the level flag can be ignored. Wait for the IRQ event triggered by FIFO_U2H_EMPTY_FLAG. Deassert the RTS after required delay; see also Section 7.3.5.6. When the RTS is deasserted, the CTS_DEASSERT bit is set. CTS_DEASSERT is an informational bit.

To receive data, set up an IRQ event based on CD_ASSERT to know when the carrier is detected and the new data bytes are expected. Also, set up the additional IRQ events to trigger each time FIFO_H2U_LEVEL_FLAG is set. Select the desired level of FIFO_H2U. Dequeue the data from FIFO_H2U every time the level exceeds the set threshold. Also, set up IRQ event trigger based on CD_DEASSERT to know when all the data have been received. At this point, monitor FIFO_H2U.EMPTY_FLAG when dequeuing each character to know when FIFO_H2U is empty and all the data bytes have been dequeued and transmitted to the microcontroller.

Alternatively, the CD pin can be directly connected to the microcontroller to monitor the status of the HART bus. In this configuration, mask CD_ASSERT flag by setting MODEM_STATUS_MASK.CD_ASSERT bit = 1 to prevent CD_ASSERT from generating an IRQ event.