JAJSNU4A May   2023  – June 2024 AFE78201 , AFE88201

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements
    7. 5.7  Timing Diagrams
    8. 5.8  Typical Characteristics: VOUT DAC
    9. 5.9  Typical Characteristics: ADC
    10. 5.10 Typical Characteristics: Reference
    11. 5.11 Typical Characteristics: Power Supply
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Digital-to-Analog Converter (DAC) Overview
        1. 6.3.1.1 DAC Resistor String
        2. 6.3.1.2 DAC Buffer Amplifier
        3. 6.3.1.3 DAC Transfer Function
        4. 6.3.1.4 DAC Gain and Offset Calibration
        5. 6.3.1.5 Programmable Slew Rate
        6. 6.3.1.6 DAC Register Structure and CLEAR State
      2. 6.3.2  Analog-to-Digital Converter (ADC) Overview
        1. 6.3.2.1 ADC Operation
        2. 6.3.2.2 ADC Custom Channel Sequencer
        3. 6.3.2.3 ADC Synchronization
        4. 6.3.2.4 ADC Offset Calibration
        5. 6.3.2.5 External Monitoring Inputs
        6. 6.3.2.6 Temperature Sensor
        7. 6.3.2.7 Self-Diagnostic Multiplexer
        8. 6.3.2.8 ADC Bypass
      3. 6.3.3  Programmable Out-of-Range Alarms
        1. 6.3.3.1 Alarm-Based Interrupts
        2. 6.3.3.2 Alarm Action Configuration Register
        3. 6.3.3.3 Alarm Voltage Generator
        4. 6.3.3.4 Temperature Sensor Alarm Function
        5. 6.3.3.5 Internal Reference Alarm Function
        6. 6.3.3.6 ADC Alarm Function
        7. 6.3.3.7 Fault Detection
      4. 6.3.4  IRQ
      5. 6.3.5  Internal Reference
      6. 6.3.6  Integrated Precision Oscillator
      7. 6.3.7  Precision Oscillator Diagnostics
      8. 6.3.8  One-Time Programmable (OTP) Memory
      9. 6.3.9  GPIO
      10. 6.3.10 Timer
      11. 6.3.11 Unique Chip Identifier (ID)
      12. 6.3.12 Scratch Pad Register
    4. 6.4 Device Functional Modes
      1. 6.4.1 Register Built-In Self-Test (RBIST)
      2. 6.4.2 DAC Power-Down Mode
      3. 6.4.3 Reset
    5. 6.5 Programming
      1. 6.5.1 Communication Setup
        1. 6.5.1.1 SPI Mode
        2. 6.5.1.2 UART Mode
      2. 6.5.2 GPIO Programming
      3. 6.5.3 Serial Peripheral Interface (SPI)
        1. 6.5.3.1 SPI Frame Definition
        2. 6.5.3.2 SPI Read and Write
        3. 6.5.3.3 Frame Error Checking
        4. 6.5.3.4 Synchronization
      4. 6.5.4 UART Interface
        1. 6.5.4.1 UART Break Mode (UBM)
      5. 6.5.5 Status Bits
      6. 6.5.6 Watchdog Timer
  8. 7 Register Maps
    1. 7.1 AFEx8201 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Multichannel Configuration
    2. 8.2 Typical Application
      1. 8.2.1 Analog Output Module
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 XTR305
            1. 8.2.1.2.1.1 Current-Output Mode
            2. 8.2.1.2.1.2 Voltage Output Mode
            3. 8.2.1.2.1.3 Diagnostic Features
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Setup
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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発注情報

7.1 AFEx8201 Registers

Complex bit access types are encoded to fit into small table cells. The following table shows the codes that are used for access types in this section.

Table 7-2 AFEx8201 Access-Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
W WO Write only
W WSC Write self clear
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When used in a register name, an offset, or an address, these variables refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
y When used in a register name, an offset, or an address, this variable refers to the value of a register array.

7.1.1 NOP Register (Offset = 0h) [Reset = 0000h]

Return to the Register Map.

Table 7-3 NOP Register Field Descriptions
Bit Field Type Reset Description
15-0 NOP WO 0h No operation.
Data written to this field have no effect. Always reads zeros.

7.1.2 DAC_DATA Register (Offset = 1h) [Reset = 0000h]

Return to the Register Map.

DAC code for VOUT.

Table 7-4 DAC_DATA Register Field Descriptions
Bit Field Type Reset Description
15-0 DATA R/W 0h Data.
DAC code for VOUT.

7.1.3 CONFIG Register (Offset = 2h) [Reset = 0036h]

Return to the Register Map.

Table 7-5 CONFIG Register Field Descriptions
Bit Field Type Reset Description
15-14 CRC_ERR_CNT R/W 0h CRC Errors Count Limit
Sets the numbers of consecutive SPI CRC frames that must have errors before the status bits is set.
0h = 1 (default); 1h = 2; 2h = 4; 3h = 8
13-10 CLKO R/W 0h CLKO Enable
Enable the CLK_OUT pin and set the divider value.
0h = CLKO disabled (default);
1h = 1.2288 MHz;
2h = 1.2288 / 2 MHz;
3h = 1.2288 / 4 MHz;
4h = 1.2288 / 8 MHz;
5h = 1.2288 / 16 MHz;
6h =1.2288 / 32 MHz;
7h = 1.2288 / 64 MHz;
8h = 1.2288 / 128 MHz;
9h = 1.2288 / 256 MHz;
Ah = 1.2288 / 512 MHz;
Bh = 1.2288 / 1024 MHz;
Ch = 1'b0; Dh = 1'b0; Eh = 1'b0;
Fh = Timer
9 UBM_IRQ_EN R/W 0h UBM IRQ Enable
Enable IRQ to be sent on UARTOUT through UBM.
0h = Disabled (default); 1h = Enabled
8 IRQ_PIN_EN R/W 0h IRQ Pin Enable
Enable IRQ pin functionality.
0h = Disabled (default); 1h = Enabled
7 CLR_PIN_EN R/W 0h Clear Input Pin Enable
Enable pin-based transition to the CLEAR state in UBM and SPI.
0h = Disabled (default); 1h = SCLR pin enabled in SPI mode or SDI pin configured as clear input pin in UBM
6 UART_DIS R/W 0h UART Disable
Disable UART functionality.
0h = UART Enabled (default); 1h = UART Disabled
5 RESERVED R 1h Reserved. Always set this bit to 1h for proper functionality.
4 CRC_EN R/W 1h CRC Enable
Enable CRC for SPI.
0h = Disabled; 1h = Enabled (default)
3 IRQ_POL R/W 0h IRQ Polarity
0h = Active low (default); 1h = Active high
2 IRQ_LVL R/W 1h IRQ Level
0h = Edge sensitive; 1h = Level sensitive (default)
1 DSDO R/W 1h SDO Hi-Z
0h = Drive SDO during CS = 0; 1h = SDO always Hi-Z (default)
0 FSDO R/W 0h Fast SDO
SDO is driven on negative edge of SCLK.
0h = drive SDO on rising edge of SCLK (launching edge) (default)
1h = drive SDO on falling edge of SCLK (capture edge 1/2 clock early)

7.1.4 DAC_CFG Register (Offset = 3h) [Reset = 0B00h]

Return to the Register Map.

Table 7-6 DAC_CFG Register Field Descriptions
Bit Field Type Reset Description
15-13 RESERVED R/W 0h
12 PD R/W 0h DAC Output Buffer Power-down

DAC output set to Hi-Z in power-down.

0h = DAC output buffer enabled (default)

1h = DAC output buffer disabled

11-9 SR_CLK R/W 5h Slew Clock Rate

0h = 307.2 kHz

1h = 153.6 kHz

2h = 76.8 kHz

3h = 38.4 kHz

4h = 19.2 kHz

5h = 9600 Hz (default)

6h = 4800 Hz

7h = 2400 Hz

8-6 SR_STEP R/W 4h Slew Step Size

0h = 1 code

1h = 2 codes

2h = 4 codes

3h = 8 codes

4h = 16 codes (default)

5h = 32 codes

6h = 64 codes

7h = 128 codes

5 SR_EN R/W 0h Slew Enable

Enables slew on the output voltage.

0h = Disabled (default)

1h = Enabled

4 SR_MODE R/W 0h Slew Mode

Output slew rate mode select.

0h = Linear Slew (default)

1h = Sinusoidal Slew

3 RESERVED R 0h
2 CLR R/W 0h CLEAR State

0h = Normal operation (default)

1h = Force the DAC to the CLEAR state
1-0 RESERVED R 0h

7.1.5 DAC_GAIN Register (Offset = 4h) [Reset = 8000h]

Return to the Register Map.

Table 7-7 DAC_GAIN Register Field Descriptions
Bit Field Type Reset Description
15-0 GAIN R/W 8000h Gain
Set the gain of the DAC output from 0.5 – 1.499985.
For example:

0000h = 0.5

8000h = 1.0 (default)

FFFFh = 1.499985

7.1.6 DAC_OFFSET Register (Offset = 5h) [Reset = 0000h]

Return to the Register Map.

Table 7-8 DAC_OFFSET Register Field Descriptions
Bit Field Type Reset Description
15-0 OFFSET R/W 0h Offset
Adjust the offset of the DAC output, 2's complement number.
For example:

0000h = 0 (default)

FFFFh = –1

7.1.7 DAC_CLR_CODE Register (Offset = 6h) [Reset = 0000h]

Return to the Register Map.

Table 7-9 DAC_CLR_CODE Register Field Descriptions
Bit Field Type Reset Description
15-0 CODE R/W 0h CLEAR State DAC Code
DAC code applied in the CLEAR state. See Section 6.3.1.6.

7.1.8 RESET Register (Offset = 7h) [Reset = 0000h]

Return to the Register Map.

Table 7-10 RESET Register Field Descriptions
Bit Field Type Reset Description
15-8 RESERVED R 0h
7-0 SW_RST WSC 0h

Software Reset

Write ADh to initiate software reset.

7.1.9 ADC_CFG Register (Offset = 8h) [Reset = 8810h]

Return to the Register Map.

Table 7-11 ADC_CFG Register Field Descriptions
Bit Field Type Reset Description
15 BUF_PD R/W 1h ADC Buffer Power-Down

0h = ADC buffer enabled; 1h = ADC buffer powered down (default)
14-8 HYST R/W 8h Hysteresis
The number of codes of hysteresis used when a threshold is exceeded for an ADC measurement of AIN0/AIN1/TEMP.
7-5 FLT_CNT R/W 0h Fault Count
Number of successive faults to trip an alarm.
Number of successive faults is programmed value + 1 (1-8 faults).
4 AIN_RANGE R/W 1h ADC Analog Input Range

Can only be set if PVDD ≥ 2.7 V to use 2.5-V range for AIN0 and AIN1 inputs.

0h = 2 × VREF; 1h = 1 × VREF (default)
3 EOC_PER_CH R/W 0h ADC End-of-Conversion for Every Channel
Sends an EOC pulse at the end of each channel instead of at the end of all the channels.

0h = EOC after last channel (default); 1h = EOC for every channel

2-1 CONV_RATE R/W 0h ADC Conversion Rate
This setting only affects the conversion rate for channels AIN0 and AIN1. Rates are based on a 76.8-kHz ADC clock. All other channels use 2560 Hz.

0h = 3840 Hz (default)

1h = 2560 Hz

2h = 1280 Hz

3h = 640 Hz

0 DIRECT_MODE R/W 0h Direct Mode Enable

0h = Auto mode (default); 1h = Direct mode

7.1.10 ADC_INDEX_CFG Register (Offset = 9h) [Reset = 0080h]

Return to the Register Map.

The ADC custom channel sequencing configuration is shown in Table 7-12.

Table 7-12 ADC_INDEX_CFG Register Field Descriptions
Bit Field Type Reset Description
15-8 RESERVED R 0h
7-4 STOP R/W 8h Custom Channel Sequencer Stop Index
CCS index to stop ADC sequence. Must be ≥ START. If not, STOP is forced to = START.

0h = OFFSET

1h = AIN0

2h = AIN1

3h = TEMP

4h = SD0 (VREF)

5h = SD1 (PVDD)

6h = SD2 (VDD)

7h = SD3 (ZTAT)

8h = SD4 (VOUT) (default)

9h through Fh = GND

3-0 START R/W 0h Custom Channel Sequencer Start Index
CCS index to start ADC sequence.

0h through Fh = Same as STOP field (0h is default)

7.1.11 TRIGGER Register (Offset = Ah) [Reset = 0000h]

Return to the Register Map.

Table 7-13 TRIGGER Register Field Descriptions
Bit Field Type Reset Description
15-4 RESERVED