JAJSNU3 December   2023 AFE782H1 , AFE882H1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements
    7. 5.7  Timing Diagrams
    8. 5.8  Typical Characteristics: VOUT DAC
    9. 5.9  Typical Characteristics: ADC
    10. 5.10 Typical Characteristics: Reference
    11. 5.11 Typical Characteristics: HART Modem
    12. 5.12 Typical Characteristics: Power Supply
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Digital-to-Analog Converter (DAC) Overview
        1. 6.3.1.1 DAC Resistor String
        2. 6.3.1.2 DAC Buffer Amplifier
        3. 6.3.1.3 DAC Transfer Function
        4. 6.3.1.4 DAC Gain and Offset Calibration
        5. 6.3.1.5 Programmable Slew Rate
        6. 6.3.1.6 DAC Register Structure and CLEAR State
      2. 6.3.2  Analog-to-Digital Converter (ADC) Overview
        1. 6.3.2.1 ADC Operation
        2. 6.3.2.2 ADC Custom Channel Sequencer
        3. 6.3.2.3 ADC Synchronization
        4. 6.3.2.4 ADC Offset Calibration
        5. 6.3.2.5 External Monitoring Inputs
        6. 6.3.2.6 Temperature Sensor
        7. 6.3.2.7 Self-Diagnostic Multiplexer
        8. 6.3.2.8 ADC Bypass
      3. 6.3.3  Programmable Out-of-Range Alarms
        1. 6.3.3.1 Alarm-Based Interrupts
        2. 6.3.3.2 Alarm Action Configuration Register
        3. 6.3.3.3 Alarm Voltage Generator
        4. 6.3.3.4 Temperature Sensor Alarm Function
        5. 6.3.3.5 Internal Reference Alarm Function
        6. 6.3.3.6 ADC Alarm Function
        7. 6.3.3.7 Fault Detection
      4. 6.3.4  IRQ
      5. 6.3.5  HART Interface
        1. 6.3.5.1  FIFO Buffers
          1. 6.3.5.1.1 FIFO Buffer Access
          2. 6.3.5.1.2 FIFO Buffer Flags
        2. 6.3.5.2  HART Modulator
        3. 6.3.5.3  HART Demodulator
        4. 6.3.5.4  HART Modem Modes
          1. 6.3.5.4.1 Half-Duplex Mode
          2. 6.3.5.4.2 Full-Duplex Mode
        5. 6.3.5.5  HART Modulation and Demodulation Arbitration
          1. 6.3.5.5.1 HART Receive Mode
          2. 6.3.5.5.2 HART Transmit Mode
        6. 6.3.5.6  HART Modulator Timing and Preamble Requirements
        7. 6.3.5.7  HART Demodulator Timing and Preamble Requirements
        8. 6.3.5.8  IRQ Configuration for HART Communication
        9. 6.3.5.9  HART Communication Using the SPI
        10. 6.3.5.10 HART Communication Using UART
        11. 6.3.5.11 Memory Built-In Self-Test (MBIST)
      6. 6.3.6  Internal Reference
      7. 6.3.7  Integrated Precision Oscillator
      8. 6.3.8  Precision Oscillator Diagnostics
      9. 6.3.9  One-Time Programmable (OTP) Memory
      10. 6.3.10 GPIO
      11. 6.3.11 Timer
      12. 6.3.12 Unique Chip Identifier (ID)
      13. 6.3.13 Scratch Pad Register
    4. 6.4 Device Functional Modes
      1. 6.4.1 DAC Power-Down Mode
      2. 6.4.2 Register Built-In Self-Test (RBIST)
      3. 6.4.3 Reset
    5. 6.5 Programming
      1. 6.5.1 Communication Setup
        1. 6.5.1.1 SPI Mode
        2. 6.5.1.2 UART Mode
        3. 6.5.1.3 SPI Plus UART Mode
        4. 6.5.1.4 HART Functionality Setup Options
      2. 6.5.2 GPIO Programming
      3. 6.5.3 Serial Peripheral Interface (SPI)
        1. 6.5.3.1 SPI Frame Definition
        2. 6.5.3.2 SPI Read and Write
        3. 6.5.3.3 Frame Error Checking
        4. 6.5.3.4 Synchronization
      4. 6.5.4 UART Interface
        1. 6.5.4.1 UART Break Mode (UBM)
          1. 6.5.4.1.1 Interface With FIFO Buffers and Register Map
      5. 6.5.5 Status Bits
      6. 6.5.6 Watchdog Timer
  8. 7 Register Maps
    1. 7.1 AFEx82H1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Multichannel Configuration
    2. 8.2 Typical Application
      1. 8.2.1 4-mA to 20-mA Current Transmitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Current Loop Control
          2. 8.2.1.2.2 HART Connections
          3. 8.2.1.2.3 Input Protection and Rectification
          4. 8.2.1.2.4 System Current Budget
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Setup
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
8.2.1.2.1 Current Loop Control

The DAC of the AFE882H1 sets an output voltage from 0 V to 2.5 V. Figure 8-4 shows the V-to-I circuit that sets the loop current from the DAC output voltage.

GUID-20230704-SS0I-DNM7-JVZP-TFQ0VKZ8W4GM-low.svg Figure 8-4 Current Loop Control for the AFE882H1 Transmitter

In this circuit, the loop current is set by the addition of the currents of V-to-I conversion from the output of VREFIO and the DAC VOUT. The current generated from these AFE882H1 outputs are analyzed separately.

First, the voltage from VREFIO is placed across a 412-kΩ resistor. This 1.25-V reference voltage creates a current that is directed into the summing node of an OPA333 amplifier that is set to ground. The voltage at LOOP– contributed from this current is calculated in Equation 10.

Equation 10. V L O O P – =   – V V R E F I O 412   k Ω × 20   k Ω =   – 1.25   V × 0.04854 = – 0.06068   V

From the feedback of the OPA333, the loop voltage from Equation 10 is placed across the 20-Ω resistor and sets the current through the loop as Equation 11 shows.

Equation 11. I L O O P _ V R E F I O = ( – V L O O P – 20   Ω   )   +   ( – V L O O P – 20   k Ω ) =   0.06068   V × ( 1 20   Ω   +   1 20   k Ω   ) =   3.037   m A

This 3-mA current acts as a starting current for the loop. When the AFE882H1 DAC output is 0 V, this is the current on the loop.

In addition to this initial current, the AFE882H1 DAC output also controls the loop current. The VOUT voltage is set across 120 kΩ of resistance (from the 20 kΩ plus 100 kΩ of series resistance). The opposite end of the 120 kΩ of resistance is set to ground by the feedback of the OPA333. Similar to the calculations in Equation 10 and Equation 11, the voltage at VOUT sets a loop current, as Equation 12 and Equation 13 show.

Equation 12. V L O O P – = – V O U T 120   k Ω   ×   20   k Ω   =   – V O U T   ×   0.1667
Equation 13. I L O O P _ V O U T = ( – V L O O P – 20   Ω   )   +   ( – V L O O P – 20   k Ω ) =   V O U T ×   0.1667   × ( 1 20   Ω   +   1 20   k Ω   )

When the DAC output voltage is set to 0 V, the contribution to the loop current is basically 0 mA. When the DAC output voltage is set to 2.5 V, the contribution to the loop current is 20.85 mA.

As mentioned previously, the total loop current is the sum of the contribution of the current created from the VREFIO voltage and the VOUT voltage. Using these voltages, the loop current has a range from 3.037 mA to 23.89 mA.

The AFE882H1 DAC output voltage is set through a 16-bit output code. Therefore, this final conversion from the DAC code to the loop current is set based on Equation 14.

Equation 14. I L O O P =   I L O O P _ V R E F I O + I L O O P _ V O U T   = 3.037   m A   +   ( D A C   C o d e × 20.85   m A 2 16 )

In 4‑mA to 20‑mA systems, the nominal output operates from 4 mA as the low output and 20 mA as the high output. However, systems sometimes use current outputs that are outside this range to indicate different error conditions. Loop currents of 3.375 mA and 21.75 mA are often used to indicate different loop errors. Table 8-1 shows different loop output currents, along with the DAC code and voltages used.

Table 8-1 DAC Voltage Output and Loop Current Based on DAC Output Codes
OUTPUT CONDITION DAC CODE DAC OUTPUT (V) LOOP CURRENT (mA)
DAC minimum 0x0000 0 3.037
Error low 0x0426 0.04051 3.375
In-range minimum 0x0BD2 0.1154 4
In-range midscale 0x6E07 1.0745 12
In-range maximum 0xD03C 2.0335 20
Error high 0xE5B7 2.2433 21.75
DAC maximum 0xFFFF 2.5 23.891

Among the passive devices included in the design, choose current-setting resistors with tight tolerances to achieve high accuracy and low drift. These resistors discussed in the previous equations are primarily responsible for setting the gain of the current loop, and therefore, the current magnitude of the loop.