JAJSNU3 December 2023 AFE782H1 , AFE882H1
PRODUCTION DATA
The HART modulator starts modulating the carrier as soon as the CTS response is asserted. If data are enqueued into FIFO_U2H before the CTS is asserted, make sure to enqueue the required preamble bytes at the beginning of the data packet in accordance with Table 6-7. The first byte is used by the HART recipient receiver to recognize the carrier and properly detect the mark-to-space transition of the start bit in the second character. Alternatively, wait for CTS_ASSERT, and give an appropriate delay while the modulator is transmitting the mark signal. Then enqueue the preamble bytes followed by the data bytes into FIFO_U2H. Monitor the level of FIFO_U2H and timely enqueue the new data to avoid transmission gap errors.
HART REQUIREMENT | FIFO_U2H STATE | AFEx82H1 BEHAVIOR | RECOMMENDED USE CASE |
---|---|---|---|
Transmit at least 6 bit times of HART signal of specified amplitude for the carrier to be detected by the receiver. | FIFO_U2H is empty. | HART modulator starts sending mark FSK signal as soon as CTS is asserted. | Wait at least 6 bit times from CTS assert before transmitting first preamble byte. Calculate the time to enqueue the data into FIFO_U2H based on the interface mode used. |
FIFO_U2H is preloaded with data. | HART modulator starts sending FIFO_U2H data as soon as CTS is asserted. | Preload FIFO_U2H with one additional preamble byte. |
Depending on the interface mode, there is a latency from the UARTIN or CS pin to the MOD_OUT pin as a result of using FIFO_U2H in the data path.
In the SPI plus UART and UBM modes, a delay of approximately 1.5 bit times (1.5 × tBAUDUART) occurs from the stop bit on the UARTIN pin until the data are enqueued into FIFO_U2H as a result of data decoding and synchronization. Figure 6-23 shows this timing.
In SPI only mode, the HART transmit data are enqueued into FIFO_U2H using FIFO_U2H_WR register. Therefore, in this mode, take the standard SPI timing into consideration while calculating the latency of the HART transmit data from the CS pin to the MOD_OUT pin. Figure 6-21 shows the HART transmit start timing for SPI mode.
The HART character contains 11 bits; therefore, a delay of approximately 11 bit times (11 × tBAUDHART) occurs from the moment the data are dequeued from FIFO_U2H until the data are fully transmitted on the MOD_OUT pin (see Figure 6-24).
Additional delay is accumulated when there is a frequency mismatch between the incoming UART_IN data and the HART data transmitted on MOD_OUT. If the UART_IN data frequency is 2% greater compared to the MOD_OUT data frequency, a delay of approximately 1 bit time is accumulated every five HART characters. Add a gap of at least 1 bit time between every five HART characters to account for this latency. Keep the request to send (RTS) asserted until the data are fully transmitted on MOD_OUT.