JAJSNC3A March   2024  – August 2024 AFE7950-SP

PRODMIX  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3概要
  5. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Transmitter Electrical Characteristics
    6. 4.6  RF ADC Electrical Characteristics
    7. 4.7  PLL/VCO/Clock Electrical Characteristics
    8. 4.8  Digital Electrical Characteristics
    9. 4.9  Power Supply Electrical Characteristics
    10. 4.10 Timing Requirements
    11. 4.11 Switching Characteristics
    12. 4.12 Typical Characteristics
      1. 4.12.1  TX Typical Characteristics 800MHz
      2. 4.12.2  TX Typical Characteristics at 1.8GHz
      3. 4.12.3  TX Typical Characteristics at 2.6GHz
      4. 4.12.4  TX Typical Characteristics at 3.5GHz
      5. 4.12.5  TX Typical Characteristics at 4.9GHz
      6. 4.12.6  TX Typical Characteristics at 8.1GHz
      7. 4.12.7  TX Typical Characteristics at 9.6GHz
      8. 4.12.8  RX Typical Characteristics at 800MHz
      9. 4.12.9  RX Typical Characteristics at 1.75-1.9GHz
      10. 4.12.10 RX Typical Characteristics at 2.6GHz
      11. 4.12.11 RX Typical Characteristics at 3.5GHz
      12. 4.12.12 RX Typical Characteristics at 4.9GHz
      13. 4.12.13 RX Typical Characteristics at 8.1GHz
      14. 4.12.14 RX Typical Characteristics at 9.6GHz
  6. 5Device and Documentation Support
    1. 5.1 ドキュメントの更新通知を受け取る方法
    2. 5.2 サポート・リソース
    3. 5.3 Trademarks
    4. 5.4 静電気放電に関する注意事項
    5. 5.5 用語集
  7. 6Revision History
  8. 7Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4.12.4 TX Typical Characteristics at 3.5GHz

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated

AFE7950-SP TX Output Power vs Frequency
Aout = -0.5dFBS, 3.5GHz Matching, included PCB and cable losses
Figure 4-118 TX Output Power vs Frequency
AFE7950-SP TX Uncalibrated Differential Gain Error vs DSA Setting and Channel at 3.5GHz
3.5GHz Matching, included PCB and cable losses
Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1
Figure 4-120 TX Uncalibrated Differential Gain Error vs DSA Setting and Channel at 3.5GHz
AFE7950-SP TX Uncalibrated Integrated Gain Error vs DSA Setting and Channel at 3.5GHz
3.5GHz Matching, included PCB and cable losses
Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Setting = 0) + (DSA Setting)
Figure 4-122 TX Uncalibrated Integrated Gain Error vs DSA Setting and Channel at 3.5GHz
AFE7950-SP TX Uncalibrated Differential Phase Error vs DSA Setting and Channel at 3.5GHz
3.5GHz Matching, included PCB and cable losses
Figure 4-124 TX Uncalibrated Differential Phase Error vs DSA Setting and Channel at 3.5GHz
AFE7950-SP TX Uncalibrated Integrated Phase Error vs DSA Setting and Channel at 3.5GHz
3.5GHz Matching, included PCB and cable losses
Figure 4-126 TX Uncalibrated Integrated Phase Error vs DSA Setting and Channel at 3.5GHz
AFE7950-SP TX Uncalibrated Differential Gain Error vs DSA Setting and Temperature at 3.5GHz
3.5GHz Matching, 1TX
Figure 4-128 TX Uncalibrated Differential Gain Error vs DSA Setting and Temperature at 3.5GHz
AFE7950-SP TX Uncalibrated Integrated Gain Error vs DSA Setting and Temperature at 3.5GHz
3.5GHz Matching, 1TX
Figure 4-130 TX Uncalibrated Integrated Gain Error vs DSA Setting and Temperature at 3.5GHz
AFE7950-SP TX Uncalibrated Differential Phase Error vs DSA setting and Temperature at 3.5GHz
3.5GHz Matching, 1TX
Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting)
Figure 4-132 TX Uncalibrated Differential Phase Error vs DSA setting and Temperature at 3.5GHz
AFE7950-SP TX Uncalibrated Integrated Phase Error vs DSA Setting and Temperature at 3.5GHz
3.5GHz Matching, 1TX
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting=0)
Figure 4-134 TX Uncalibrated Integrated Phase Error vs DSA Setting and Temperature at 3.5GHz
AFE7950-SP TX NSD vs DSA Setting at 3.5GHz
A.
fDAC =11796.48MSPS, interleave mode, matching at 3.5GHz, Aout = –13 dBFS.
Figure 4-136 TX NSD vs DSA Setting at 3.5GHz
AFE7950-SP TX IMD3 vs Digital Amplitude and Channel at 3.5GHz
20MHz tone spacing, 3.5GHz Matching
Figure 4-138 TX IMD3 vs Digital Amplitude and Channel at 3.5GHz
AFE7950-SP TX 20MHz LTE ACPR vs DSA Setting at 3.5GHz
3.5GHz Matching, single carrier 20MHz BW TM1.1 LTE
Figure 4-140 TX 20MHz LTE ACPR vs DSA Setting at 3.5GHz
AFE7950-SP TX 20MHz LTE ACPR vs Digital Level at 3.5GHz
3.5GHz Matching, single carrier 20MHz BW TM1.1 LTE
Figure 4-142 TX 20MHz LTE ACPR vs Digital Level at 3.5GHz
AFE7950-SP TX Single Tone HD2 vs Frequency and Digital Level at 3.5GHz
Matching at 3.5GHz, fDAC = 11.79648GSPS, interleave mode, normalized to output power at harmonic frequency
Figure 4-144 TX Single Tone HD2 vs Frequency and Digital Level at 3.5GHz
AFE7950-SP TX Single Tone (–1dBFS) Output Spectrum at 3.5GHz (0 - fDAC)
Matching at 3.5GHz, fDAC = 11.79648GSPS, interleave mode.
Figure 4-146 TX Single Tone (–1dBFS) Output Spectrum at 3.5GHz (0 - fDAC)
AFE7950-SP TX Single Tone (–12dBFS) Output Spectrum at 3.5GHz (0-fDAC)
Matching at 3.5GHz, fDAC = 11.79648GSPS, interleave mode.
Figure 4-148 TX Single Tone (–12dBFS) Output Spectrum at 3.5GHz (0-fDAC)
AFE7950-SP TX Output Power vs DSA Setting at 3.5GHz
Aout = -0.5dFBS, 3.5GHz Matching, included PCB and cable losses
Figure 4-119 TX Output Power vs DSA Setting at 3.5GHz
AFE7950-SP TX Calibrated Differential Gain Error vs DSA Setting and Channel at 3.5GHz
3.5GHz Matching, included PCB and cable losses
Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1
Figure 4-121 TX Calibrated Differential Gain Error vs DSA Setting and Channel at 3.5GHz
AFE7950-SP TX Calibrated Integrated Gain Error vs DSA Setting and Channel at 3.5GHz
3.5GHz Matching, included PCB and cable losses
Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Setting = 0) + (DSA Setting)
Figure 4-123 TX Calibrated Integrated Gain Error vs DSA Setting and Channel at 3.5GHz
AFE7950-SP TX Calibrated Differential Phase Error vs DSA Setting and Channel at 3.5GHz
3.5GHz Matching, included PCB and cable losses
Phase DNL spike may occur at any DSA setting.
Figure 4-125 TX Calibrated Differential Phase Error vs DSA Setting and Channel at 3.5GHz
AFE7950-SP TX Calibrated Integrated Phase Error vs DSA Setting and Channel at 3.5GHz
3.5GHz Matching, included PCB and cable losses
Figure 4-127 TX Calibrated Integrated Phase Error vs DSA Setting and Channel at 3.5GHz
AFE7950-SP TX Calibrated Differential Gain Error vs DSA Setting and Temperature at 3.5GHz
3.5GHz Matching, 1TX, Calibrated at 25°C
Figure 4-129 TX Calibrated Differential Gain Error vs DSA Setting and Temperature at 3.5GHz
AFE7950-SP TX Calibrated Integrated Gain Error vs DSA Setting and Temperature at 3.5GHz
3.5GHz Matching, 1TX, Calibrated at 25°C
Figure 4-131 TX Calibrated Integrated Gain Error vs DSA Setting and Temperature at 3.5GHz
AFE7950-SP TX Calibrated Differential Phase Error vs DSA Setting and Temperature at 3.5GHz
3.5GHz Matching, 1TX, Calibrated at 25°C
Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting)
Figure 4-133 TX Calibrated Differential Phase Error vs DSA Setting and Temperature at 3.5GHz
AFE7950-SP TX Calibrated Integrated Phase Error vs DSA Setting and Temperature at 3.5GHz
3.5GHz Matching, 1TX, Calibrated at 25°C
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0)
Figure 4-135 TX Calibrated Integrated Phase Error vs DSA Setting and Temperature at 3.5GHz
AFE7950-SP TX IMD3 vs DSA Setting at 3.5GHz
20MHz tone spacing, 3.5GHz Matching, –13 dBFS each tone, included PCB and cable losses
Figure 4-137 TX IMD3 vs DSA Setting at 3.5GHz
AFE7950-SP TX 20MHz LTE Output Spectrum at 3.5GHz (Band 42)
3.5GHz Matching, single carrier 20MHz BW TM1.1 LTE
Figure 4-139 TX 20MHz LTE Output Spectrum at 3.5GHz (Band 42)
AFE7950-SP TX 20MHz LTE alt-ACPR vs DSA Setting at 3.5GHz
3.5GHz Matching, single carrier 20MHz BW TM1.1 LTE
Figure 4-141 TX 20MHz LTE alt-ACPR vs DSA Setting at 3.5GHz
AFE7950-SP TX 20MHz LTE alt-ACPR vs Digital Level at 3.5GHz
3.5GHz Matching, single carrier 20MHz BW TM1.1 LTE
Figure 4-143 TX 20MHz LTE alt-ACPR vs Digital Level at 3.5GHz
AFE7950-SP TX Single Tone HD3 vs Frequency and Digital Level at 3.5GHz
Matching at 3.5GHz, fDAC = 11.79648GSPS, interleave mode, normalized to output power at harmonic frequency. Dip is due to HD3 falling near DC.
Figure 4-145 TX Single Tone HD3 vs Frequency and Digital Level at 3.5GHz
AFE7950-SP TX Single Tone (–6dBFS) Output Spectrum at 3.5GHz (0-fDAC)
Matching at 3.5GHz, fDAC = 11.79648GSPS, interleave mode.
Figure 4-147 TX Single Tone (–6dBFS) Output Spectrum at 3.5GHz (0-fDAC)