JAJSN92 December   2022 AFE78101 , AFE88101

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Timing Diagrams
    8. 6.8  Typical Characteristics: VOUT DAC
    9. 6.9  Typical Characteristics: ADC
    10. 6.10 Typical Characteristics: Reference
    11. 6.11 Typical Characteristics: Power Supply
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converter (DAC) Overview
        1. 7.3.1.1 DAC Resistor String
        2. 7.3.1.2 DAC Buffer Amplifier
        3. 7.3.1.3 DAC Transfer Function
        4. 7.3.1.4 DAC Gain and Offset Calibration
        5. 7.3.1.5 Programmable Slew Rate
        6. 7.3.1.6 DAC Register Structure and CLEAR State
      2. 7.3.2 Analog-to-Digital Converter (ADC) Overview
        1. 7.3.2.1 ADC Operation
        2. 7.3.2.2 ADC Custom Channel Sequencer
        3. 7.3.2.3 ADC Synchronization
        4. 7.3.2.4 ADC Offset Calibration
        5. 7.3.2.5 External Monitoring Inputs
        6. 7.3.2.6 Temperature Sensor
        7. 7.3.2.7 Self-Diagnostic Multiplexer
        8. 7.3.2.8 ADC Bypass
      3. 7.3.3 Programmable Out-of-Range Alarms
        1. 7.3.3.1 Alarm Action Configuration Register
        2. 7.3.3.2 Alarm Voltage Generator
        3. 7.3.3.3 Temperature Sensor Alarm Function
        4. 7.3.3.4 Internal Reference Alarm Function
        5. 7.3.3.5 ADC Alarm Function
        6. 7.3.3.6 Fault Detection
      4. 7.3.4 IRQ
      5. 7.3.5 Internal Reference
      6. 7.3.6 Integrated Precision Oscillator
      7. 7.3.7 One-Time Programmable (OTP) Memory
    4. 7.4 Device Functional Modes
      1. 7.4.1 DAC Power-Down Mode
      2. 7.4.2 Reset
    5. 7.5 Programming
      1. 7.5.1 Communication Setup
        1. 7.5.1.1 SPI Mode
        2. 7.5.1.2 UART Mode
      2. 7.5.2 Serial Peripheral Interface (SPI)
        1. 7.5.2.1 SPI Frame Definition
        2. 7.5.2.2 SPI Read and Write
        3. 7.5.2.3 Frame Error Checking
        4. 7.5.2.4 Synchronization
      3. 7.5.3 UART
        1. 7.5.3.1 UART Break Mode (UBM)
      4. 7.5.4 Status Bits
      5. 7.5.5 Watchdog Timer
    6. 7.6 Register Maps
      1. 7.6.1 AFEx8101 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Multichannel Configuration
    2. 8.2 Typical Application
      1. 8.2.1 4-mA to 20-mA Current Transmitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Start-Up Circuit
          2. 8.2.1.2.2 Current Loop Control
          3. 8.2.1.2.3 Input Protection and Rectification
          4. 8.2.1.2.4 System Current Budget
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

all minimum and maximum values at TA = –40°C to +125°C and all typical values at TA = 25°C, PVDD = VDD = IOVDD = 1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOUT DAC STATIC PERFORMANCE
Resolution AFE88101 16 Bits
AFE78101 14
INL Integral nonlinearity(1) AFE88101 –4 4 LSB
AFE78101 –2 2
DNL Differential nonlinearity(1) –1 1 LSB
TUE Total unadjusted error(1) TA = –40°C to +125°C –0.07 0.07 %FSR
TA = –40°C to +85°C –0.05 0.05
TA = 25°C –0.04 0.04
ZCE Zero code error TA = –40°C to +125°C –0.07 0.07 %FSR
TA = –40°C to +85°C –0.05 0.05
TA = 25°C –0.03 0.03
ZCE-TC Zero code error temperature coefficient ±3 ppm/°C
OE Offset error(1) TA = –40°C to +125°C –0.07 0.07 %FSR
TA = –40°C to +85°C –0.05 0.05
TA = 25°C –0.03 0.03
OE-TC Offset error temperature coefficient (1) ±3 ppm/°C
GE Gain error(1) TA = –40°C to +125°C –0.04 0.04 %FSR
TA = –40°C to +85°C –0.04 0.04
TA = 25°C –0.03 0.03
GE-TC Gain error temperature coefficient(1) ±3 ppm FSR/°C
FSE Full-scale error TA = –40°C to +125°C –0.07 0.07 %FSR
TA = –40°C to +85°C –0.06 0.06
TA = 25°C –0.04 0.04
FSE-TC Full-scale error temperature coefficient ±3 ppm FSR/°C
VOUT DAC DYNAMIC PERFORMANCE
ts Output voltage settling time(4) ¼ to ¾ scale and ¾ to ¼ scale settling to ±2 LSB,
PVDD = VDD = 1.8 V, VREFIO = 1.25 V		 65 µs
10-mV step settling to ±2 LSB,
PVDD = VDD = 1.8 V, VREFIO = 1.25 V		 30
SR Slew rate(4) Fullscale transition measured from 10% to 90% 2 V/µs
Vn Output noise(4) 0.1 Hz to 10 Hz, DAC at midscale,
PVDD = VDD = 1.8 V, VREFIO = 1.25 V		 0.25 LSBPP
100-kHz bandwidth, DAC at midscale,
PVDD = VDD = 1.8 V, VREFIO = 1.25 V		 32 µVrms
Vn Output noise density Measured at 1 kHz, DAC at midscale,
PVDD = VDD = 1.8 V, VREFIO = 1.25 V		 180 nV/√Hz
Measured at 1 kHz, DAC at midscale,
PVDD = 5 V, VREFIO = 1.25 V		 260
Power supply rejection ratio (AC) 200-mV 50-Hz to 60-Hz sine wave superimposed on power supply voltage, DAC at midscale. 85 dB
Code change glitch impulse Midcode ±1 LSB (including feedthrough)
PVDD = VDD = 1.8 V, VREFIO = 1.25 V		 4.5 nV-s
Code change glitch magnitude Midcode ±1 LSB (including feedthrough)
PVDD = 5 V, VREFIO = 1.25 V		 1.5 mV
Digital feedthrough At SCLK = 1 MHz, DAC output at midscale 1 nV-s
VOUT DAC OUTPUT CHARACTERISTICS
Output voltage range RANGE = 0, PVDD = VDD 0.15 1.25 V
RANGE = 1, PVDD = VDD 0.2 1.0
RANGE = 0, PVDD > 2.7 V, VDD generated 0.3 2.5
RANGE = 1, PVDD > 2.7 V, VDD generated 0.4 2.0
VOUT alarm output high PVDD > 2.7 V, VDD internally generated –6% 2.5 +6% V
PVDD = VDD –6% 1.25 +6%
VOUT alarm output low PVDD > 2.7 V, VDD internally generated –5% 0.3 +5% V
PVDD = VDD –5% 0.15 +5%
RLOAD Resistive load(2) 10 kΩ
CLOAD Capacitive load(2) 100 pF
Load regulation DAC at midscale, –1 mA ≤ IOUT ≤ +1 mA 10 µV/mA
Short-circuit current Full scale output shorted to GND 5 mA
Zero output shorted to VDD 5
Output voltage headroom to PVDD DAC at full code, IOUT = 1 mA (sourcing) 200 mV
Output voltage footroom to GND DAC at zero code, IOUT = 1 mA (sinking) 200 mV
ZO DC small signal output impedance DAC at midscale 10 mΩ
Output Hi-Z 500 kΩ
Power supply rejection ratio (dc) DAC at midscale; PVDD = 1.8 V ± 10% 0.1 mV/V
Output voltage drift vs time, 1000 hours TA = 35°C, VOUT = midscale, ideal VREF ±5 ppm FSR
DIAGNOSTIC ADC
Input voltage range PVDD = VDD 0 1.25 V
PVDD > 2.7 V 0 2.5
Resolution 12 Bits
DNL Differential nonlinearity Specified 12-bit monotonic –1 ±0.2 1 LSB
INL Integral nonlinearity –4 ±1 4 LSB
OE Offset error After calibration –10 ±1.6 10 LSB
GE Gain error –0.8 ±0.13 0.8 %FSR
Noise ±4 LSB
Input capacitance 6 pF
Input bias current ADC not converting –50 50 nA
Acquisition time 52 µs
Conversion time 210 µs
Conversion rate 3.84 kSPS
Temperature sensor accuracy 5 °C
INTERNAL OSCILLATOR
Frequency TA = –40°C to +125°C 1.2165 1.2288 1.2411 MHz
VOLTAGE REFERENCE INPUT
ZVREFIO Reference input impedance (VREFIO) RANGE = 0 125 kΩ
RANGE = 1 180
CVREFIO Reference input capacitance (VREFIO) 100 pF
VOLTAGE REFERENCE OUTPUT
Output (initial accuracy)(3) TA = 25°C 1.248 1.25 1.252 V
Output drift(3) TA = –40°C to +125°C 10 ppm/℃
Output impedance(3) 0.1 Ω
Output noise(3) 0.1 Hz to 10 Hz 7.5 µVPP
Output noise density(3) Measured at 10 kHz, reference load = 100 nF 200 nV/√Hz
Load current(3) Sourcing, 0.1% VREF change from nominal 2.5 mA
Sinking, 0.1% VREF change from nominal 0.3
Load regulation(3) Sourcing, 0 mA to 2.5 mA 4 µV/mA
COUT Stable output capacitance TA = –40°C to +125°C, 
ESR from 10 mΩ to 400 mΩ		 70 100 130 nF
Line regulation(3) 80 µV/V
Output voltage drift vs time(3) TA = 35°C, 1000 hours ±100 ppm
Thermal hysteresis(3) 1st cycle 500 µV
Additional cycles 25 µV
VDD VOLTAGE REGULATOR OUTPUT
Output voltage 1.71 1.8 1.89 V
Output impedance(3) PVDD = 3.3 V, sourcing, 0.5 mA to 2.5 mA 3 Ω
Load current(3) PVDD = 3.3 V, sourcing, 1% VDD change from nominal 4 mA
THERMAL ALARM
Alarm trip point 130 °C
Warning trip point 85 °C
Hysteresis 12 °C
Trip point absolute accuracy 5 °C
Trip point relative accuracy 2 °C
DIGITAL INPUT CHARACTERISTICS
VIH High-level input voltage 0.7 V/IOVDD
VIL Low-level input voltage 0.3 V/IOVDD
Hysteresis voltage 0.05 V/IOVDD
Input current –400 400 nA
Pin capacitance Per pin 10 pF
DIGITAL OUTPUT CHARACTERISTICS
VOH High-level output voltage ISOURCE = 1 mA 0.8 V/IOVDD
VOL Low-level output voltage ISINK = 1 mA 0.2 V/IOVDD
VOL Open-drain low-level output voltage ISINK = 2 mA 0.3 V
Output pin capacitance 10 pF
POWER REQUIREMENTS
IPVDD Current flowing into PVDD PVDD only, VDD internally generated, DAC at zero-scale, ADC and SPI static, internal reference 170 210 µA
Shared PVDD and VDD connection, DAC at zero-scale, ADC and SPI static 32 45
ILDO VDD LDO quiescent current From PVDD 8 µA
IVDD Current flowing into VDD Shared PVDD and VDD connection, DAC at zero-scale, ADC and SPI static, internal reference 130 160 µA
IREFIO Internal reference current consumption From external or internally generated VDD 52 70 µA
IADC ADC current consumption From PVDD, ADC converting at 3.84 kSPS 10 µA
CVDD Recommended VDD decoupling capacitance 1 10 µF
IIOVDD Current flowing into IOVDD SPI static 5 20 µA
IVREFIO Current flowing into VREFIO 0.15-V to 1.25-V range, midscale code 10 µA
(1) End point fit between code 0 to code 65,535 for 16-bit, code 0 to code 16,383 for 14-bit, DAC output unloaded, performance under resistive and capacitive load conditions are specified by design and characterization.
(2) Not production tested.
(3) Derived from the characterization data.
(4) Output buffer gain (G) = 2, PVDD > 2.7 V.