JAJSQ19 march 2023 AFE781H1 , AFE881H1
PRODUCTION DATA
The integration of receive and transmit FIFOs for HART communication enables easy scalability in multichannel configurations using the SPI only interface. Because CS low is required for communication and SDO can be set to a tri-state condition, only individual CS signals are required from the microcontroller for all the AFEx81H1 devices in the system. The SDI, SDO, and SCLK signals can be combined. All the individual ALARM pins can be wired-OR together. This minimizes the number of microcontroller GPIO signals required for communication, as well as the number of isolation channels for isolated systems. The multichannel configuration block diagram is shown in Figure 8-39.