JAJSQ19 march   2023 AFE781H1 , AFE881H1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 説明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Timing Diagrams
    8. 6.8  Typical Characteristics: VOUT DAC
    9. 6.9  Typical Characteristics: ADC
    10. 6.10 Typical Characteristics: Reference
    11. 6.11 Typical Characteristics: HART Modem
    12. 6.12 Typical Characteristics: Power Supply
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converter (DAC) Overview
        1. 7.3.1.1 DAC Resistor String
        2. 7.3.1.2 DAC Buffer Amplifier
        3. 7.3.1.3 DAC Transfer Function
        4. 7.3.1.4 DAC Gain and Offset Calibration
        5. 7.3.1.5 Programmable Slew Rate
        6. 7.3.1.6 DAC Register Structure and CLEAR State
      2. 7.3.2 Analog-to-Digital Converter (ADC) Overview
        1. 7.3.2.1 ADC Operation
        2. 7.3.2.2 ADC Custom Channel Sequencer
        3. 7.3.2.3 ADC Synchronization
        4. 7.3.2.4 ADC Offset Calibration
        5. 7.3.2.5 External Monitoring Inputs
        6. 7.3.2.6 Temperature Sensor
        7. 7.3.2.7 Self-Diagnostic Multiplexer
        8. 7.3.2.8 ADC Bypass
      3. 7.3.3 Programmable Out-of-Range Alarms
        1. 7.3.3.1 Alarm-Based Interrupts
        2. 7.3.3.2 Alarm Action Configuration Register
        3. 7.3.3.3 Alarm Voltage Generator
        4. 7.3.3.4 Temperature Sensor Alarm Function
        5. 7.3.3.5 Internal Reference Alarm Function
        6. 7.3.3.6 ADC Alarm Function
        7. 7.3.3.7 Fault Detection
      4. 7.3.4 IRQ
      5. 7.3.5 HART Interface
        1. 7.3.5.1  FIFO Buffers
          1. 7.3.5.1.1 FIFO Buffer Access
          2. 7.3.5.1.2 FIFO Buffer Flags
        2. 7.3.5.2  HART Modulator
        3. 7.3.5.3  HART Demodulator
        4. 7.3.5.4  HART Modem Modes
          1. 7.3.5.4.1 Half-Duplex Mode
          2. 7.3.5.4.2 Full-Duplex Mode
        5. 7.3.5.5  HART Modulation and Demodulation Arbitration
          1. 7.3.5.5.1 HART Receive Mode
          2. 7.3.5.5.2 HART Transmit Mode
        6. 7.3.5.6  HART Modulator Timing and Preamble Requirements
        7. 7.3.5.7  HART Demodulator Timing and Preamble Requirements
        8. 7.3.5.8  IRQ Configuration for HART Communication
        9. 7.3.5.9  HART Communication Using the SPI
        10. 7.3.5.10 HART Communication Using UART
        11. 7.3.5.11 Memory Built-In Self-Test (MBIST)
      6. 7.3.6 Internal Reference
      7. 7.3.7 Integrated Precision Oscillator
      8. 7.3.8 One-Time Programmable (OTP) Memory
    4. 7.4 Device Functional Modes
      1. 7.4.1 DAC Power-Down Mode
      2. 7.4.2 Reset
    5. 7.5 Programming
      1. 7.5.1 Communication Setup
        1. 7.5.1.1 SPI Mode
        2. 7.5.1.2 UART Mode
        3. 7.5.1.3 SPI Plus UART Mode
        4. 7.5.1.4 HART Functionality Setup Options
      2. 7.5.2 Serial Peripheral Interface (SPI)
        1. 7.5.2.1 SPI Frame Definition
        2. 7.5.2.2 SPI Read and Write
        3. 7.5.2.3 Frame Error Checking
        4. 7.5.2.4 Synchronization
      3. 7.5.3 UART Interface
        1. 7.5.3.1 UART Break Mode (UBM)
          1. 7.5.3.1.1 Interface With FIFO Buffers and Register Map
      4. 7.5.4 Status Bits
      5. 7.5.5 Watchdog Timer
    6. 7.6 Register Maps
      1. 7.6.1 AFEx81H1 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Multichannel Configuration
    2. 8.2 Typical Application
      1. 8.2.1 4-mA to 20-mA Current Transmitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Start-Up Circuit
          2. 8.2.1.2.2 Current Loop Control
          3. 8.2.1.2.3 Input Protection and Rectification
          4. 8.2.1.2.4 System Current Budget
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 Register Maps

Table 7-13 lists the memory-mapped registers for the AFEx81H1 registers. Consider all register offset addresses not listed in Table 7-13 as reserved locations; do not modify these register contents.

Table 7-13 Register Map
ADDR (HEX) REGISTER BIT DESCRIPTION
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00h NOP NOP [15:0]
01h DAC_DATA DATA [15:0]
02h CONFIG RESERVED CRC_ERR_CNT [1:0] CLKO_DIV CLKO_EN RESERVED UBM_
IRQ_EN		 IRQ_
PIN_EN		 CLR_
PIN_EN		 UART_DIS UART_
BAUD		 CRC_EN IRQ_POL IRQ_LVL DSDO FSDO
03h DAC_CFG RESERVED PD SR_CLK [2:0] SR_STEP [2:0] SR_EN SR_MODE RESERVED CLR CLR_
RANGE		 RANGE
04h DAC_GAIN GAIN [15:0]
05h DAC_OFFSET OFFSET [15:0]
06h DAC_CLR_
CODE 		CODE [15:0]
07h RESET RESERVED SW_RST [7:0]
08h ADC_CFG BUF_PD HYST [6:0] FLT_CNT [2:0] AIN_
RANGE		 EOC_
PER_CH		 CONV_RATE [1:0] DIRECT_
MODE
09h ADC_INDEX_
CFG 		RESERVED STOP [3:0] START [3:0]
0Ah TRIGGER RESERVED MBIST SHADOW
LOAD		 ADC
0Bh SPECIAL_
CFG(1)		 RESERVED OTP_
LOAD_
SW_RST		 ALMV_
POL		 AIN1_ENB
0Eh MODEM_CFG Tx2200Hz RESERVED DUPLEX_
EXT		 RX_
HORD_EN		 RX_EXT
FILT_EN		 TxRES TxAMP [4:0] HART_EN DUPLEX TxHPD RTS
0Fh FIFO_CFG RESERVED FIFO_H2U_FLUSH FIFO_U2H_FLUSH H2U_LEVEL_SET [3:0] U2H_LEVEL_SET [3:0]
10h ALARM_ACT SD_FLT [1:0] TEMP_FLT [1:0] AIN1_FLT [1:0] AIN0_FLT [1:0] CRC_WDT_FLT [1:0] VREF_FLT [1:0] THERM_ERR_FLT [1:0] THERM_WARN_FLT [1:0]
11h WDT RESERVED WDT_UP [2:0] WDT_LO [1:0] WDT_EN
12h AIN0_
THRESHOLD 		Hi [7:0] Lo [7:0]
13h AIN1_
THRESHOLD 		Hi [7:0] Lo [7:0]
14h TEMP_
THRESHOLD 		Hi [7:0] Lo [7:0]
15h FIFO_U2H_WR RESERVED PARITY DATA [7:0]
16h UBM(2) RESERVED REG_
MODE
1Dh ALARM_
STATUS_MASK 		RESERVED SD_FLT OSC_FAIL RESERVED OTP_
CRC_ERR		 CRC_FLT WD_FLT VREF_FLT ADC_
AIN1_FLT		 ADC_
AIN0_FLT		 ADC_
TEMP_
FLT		 THERM_
ERR_FLT		 THERM_
WARN_
FLT
1Eh GEN_
STATUS_MASK 		RESERVED MBIST_
DONE		 MBIST_
FAIL		 RESERVED SR_
BUSYn		 ADC_
EOC		 RESERVED BREAK_
FRAME_
ERR		 BREAK_
PARITY_
ERR		 UART_
FRAME_
ERR		 UART_
PARITY_
ERR
1Fh MODEM_
STATUS_MASK 		RESERVED GAP_
ERR		 FRAME_
ERR		 PARITY_
ERR		 FIFO_H2U
_LEVEL_
FLAG		 FIFO_H2U
_FULL_
FLAG		 FIFO_H2U
_EMPTY_
FLAG		 FIFO_U2H
_LEVEL_
FLAG		 FIFO_U2H
_FULL_
FLAG		 FIFO_U2H
_EMPTY_
FLAG		 CD_DE
ASSERT		 CD_
ASSERT		 CTS_DE
ASSERT		 CTS_
ASSERT
20h ALARM_
STATUS 		GEN_
IRQ		 MODEM_
IRQ		 SD_FLT OSC_FAIL CRC_CNT [1:0] OTP_
LOADEDn		 OTP_
CRC_ERR		 CRC_FLT WD_FLT VREF_FLT ADC_
AIN1_FLT		 ADC_
AIN0_FLT		 ADC_
TEMP_
FLT		 THERM_
ERR_FLT		 THERM_
WARN_
FLT
21h GEN_
STATUS 		ALARM_
IRQ		 MODEM_
IRQ		 RESERVED OTP_
BUSY		 RESERVED MBIST_
DONE		 MBIST_
FAIL		 RESET SR_
BUSYn		 ADC_
EOC		 ADC_
BUSY		 PVDD_HI BREAK_
FRAME_
ERR		 BREAK_
PARITY_
ERR		 UART
_FRAME
_ERR		 UART_
PARITY_
ERR
22h MODEM_
STATUS 		ALARM_
IRQ		 GEN_
IRQ		 RESERVED GAP_
ERR		 FRAME_
ERR		 PARITY
_ERR		 FIFO_H2U
_LEVEL_
FLAG		 FIFO_H2U
_FULL_
FLAG		 FIFO_H2U
_EMPTY_
FLAG		 FIFO_U2H
_LEVEL_
FLAG		 FIFO_U2H
_FULL_
FLAG		 FIFO_U2H
_EMPTY_
FLAG		 CD_DE
ASSERT		 CD_
ASSERT		 CTS_DE
ASSERT		 CTS_
ASSERT
23h ADC_FLAGS RESERVED SD4_FAIL SD3_FAIL SD2_FAIL SD1_FAIL SD0_FAIL TEMP_
FAIL		 AIN1_
FAIL		 AIN0_
FAIL		 RESERVED
24h ADC_AIN0 RESERVED DATA [11:0]
25h ADC_AIN1 RESERVED DATA [11:0]
26h ADC_TEMP RESERVED DATA [11:0]
27h ADC_SD_MUX RESERVED DATA [11:0]
28h ADC_OFFSET RESERVED DATA [11:0]
2Ah FIFO_H2U_RD LEVEL [3:0] LEVEL_
FLAG		 FULL_
FLAG		 EMPTY_
FLAG		 PARITY DATA [7:0]
2Bh FIFO_STATUS H2U_LEVEL [3:0] H2U
_LEVEL_
FLAG		 H2U
_FULL_
FLAG		 H2U
_EMPTY_
FLAG		 RESERVED U2H_LEVEL [3:0] U2H
_LEVEL_
FLAG		 U2H
_FULL_
FLAG		 U2H
_EMPTY_
FLAG		 RESERVED
2Ch DAC_OUT DATA [15:0]
2Dh ADC_OUT RESERVED DATA [11:0]
2Eh ADC_BYP DATA_
BYP_EN		 OFST_
BYP_EN		 DIS_GND_
SAMP		 RESERVED DATA [11:0]
2Fh FORCE_FAIL CRC_FLT VREF_FLT THERM_
ERR_FLT		 THERM_
WARN_
FLT		 RESERVED SD4_HI_
FLT		 SD4_LO_
FLT		 SD3_HI_
FLT		 SD3_LO_
FLT		 SD2_HI_
FLT		 SD2_LO_
FLT		 SD1_HI_
FLT		 SD1_LO_
FLT		 SD0_HI_
FLT		 SD0_LO_
FLT
(1) The SPECIAL_CFG register can only be reset with POR, and does not respond to the RESET pin or SW_RST command.
(2) The UBM register can only be accessed with a UBM command.